Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2000-06-20
2001-12-25
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S200000
Reexamination Certificate
active
06333887
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to circuits and methods for selectively coupling redundant elements into an integrated circuit.
BACKGROUND OF THE INVENTION
An integrated circuit is a complete electronic circuit, containing transistors, diodes, resistors, and capacitors, along with their interconnecting electrical conductors, e.g., input/output (I/O) lines, contained entirely within a single chip of silicon. Integrated circuits continue to decrease in size, and the circuits they contain continue to increase in complexity. This increases the chances of defective chips resulting from a failed element or a defective conductor.
One way to reduce semiconductor scrap is to provide redundant elements on the integrated circuits. That way, if a primary element is defective a redundant element can be substituted in its place. One area which can benefit from the use of redundancy is with I/O lines of, for example, a memory circuit. Typical memory circuits comprise millions of equivalent memory cells arranged in addressable rows and columns. Modern memory blocks can include as many as 128 or more pair of I/O lines accessing a four (4) mega-bit block of memory. If one or more of these pairs of I/O lines is inoperable, then usable memory space becomes un-accessible.
Early techniques to ameliorate this situation included global re-routing to another location on or off the memory circuit chip. Global re-routing is achieved by using a replacement pair of I/O lines to address a replacement portion of memory. Replacing the defective I/O pair typically comprises opening fuse-type circuits to ‘program’ a redundant I/O pair to respond. However, the replacement I/O and the replacement portion of memory require chip space. The cost of the chip space required by global re-routing was acceptable when I/O lines addressed a smaller number of columns. Now, however, providing additional memory blocks at other locations on or off the chip is very costly. Additionally, the timing between addressing sequences must be adjusted for the re-routing delay. This slows the operation of the memory. Thus, the global re-routing scheme requires circuitry which adversely effects the available real estate and slows the operation of the memory.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for circuits and methods to replace inoperative I/O lines without consuming valuable chip space or creating an operating time penalty.
SUMMARY OF THE INVENTION
The above mentioned problems with redundancy repair schemes and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A repair scheme is described which selectively couples redundant elements into an integrated circuit.
In particular, an illustrative embodiment of the present invention includes an input/output repair circuit. The input/output repair circuit includes a fuse bank. The fuse bank has multiple fuses which are programmed in either a first or a second state. A logic/select circuit couples to the fuse bank. A number of multiplexors couple to the fuse bank through the logic/select circuit. A number of first input/output lines couple to the number of multiplexors. There are a number of second input/output lines. Each of the number of second input/output lines selectively couple to the number of multiplexors. The number of second input/output lines is greater than the number of first input/output lines. Thus, the number of second input/output lines include at least one redundant line that can be selectively coupled to the first input/output lines through the multiplexers when necessary to “repair out” or “replace” a defective input/output line. The multiplexers effectively isolate the defective input/output line by not coupling the defective line to one of the first input/output lines. Further, the multiplexers shift the connections for a portion of the first input/output lines to adjacent second input/output lines for each the second input/output lines between the defective second input/output line and the redundant input/output line.
In another embodiment, a memory circuit is provided. The memory circuit includes multiple rows of wordlines within a memory block. The memory circuit has multiple columns of bitlines also within the memory block. The intersection of the multiple rows of wordlines and multiple columns of bitlines have memory cells.
A number of sense amplifiers couple to the multiple columns of bitlines. A column decoder couples to the number of sense amplifiers. A number of local input/output lines couple to the multiple columns of bitlines through the column decoder. There are a number of global input/output lines. A number of multiplexors couple the number of local input/output lines to the number of global input/output lines. There is a fuse bank which has a number of fuses. Each fuse within the fuse bank is programmed to a first state or a second state. A logic/select circuit couples the fuse bank to the number of multiplexors such that the state of the fuse determines the coupling between the number of local input/output lines to the number of global input/output lines.
In another embodiment, a method for replacing inoperable input/output lines in a memory circuit is provided. The method includes reading a number of fuses in a fuse bank. Each fuse is programmed to a first or a second state. The fuses are associated with a number of multiplexors. The state of the fuse is passed from the number fuses through a logic/select circuit and to the number of multiplexors. At least one of the number of multiplexors is caused to switch the coupling between a global input/output line and a number of local input/output lines when the fuse associated with the multiplexor is programmed to the second state.
In another embodiment, a method for replacing inoperable input/output lines in a memory circuit is provided. The method includes reading the state of a number of programmed fuses. The number of programmed fuses are associated with a number of multiplexors. Each of the number of multiplexors couples a global input/output line to a number of local input/output lines. When at least one of the fuses is programmed to indicate that one of the number of local input/output lines coupled to one of the number of multiplexors is inoperable, that input/output line is replaced with an adjacent local input/output line.
In another embodiment, an information handling system is provided. The information handling system includes a central processing unit. A random access memory is also provided. The random access memory includes multiple rows of wordlines within a memory block. The random access memory has multiple columns of bitlines also within the memory block. The intersection of the multiple rows of wordlines and multiple columns of bitlines have memory cells. A number of sense amplifiers couple to the multiple columns of bitlines. A column decoder couples to the number of sense amplifiers. A number of local input/output lines couple to the multiple columns of bitlines through the column decoder. There are a number of global input/output lines. A number of multiplexors couple the number of local input/output lines to the number of global input/output lines. There is a fuse bank which has a number of fuses. Each fuse within the fuse bank is programmed to a first state or a second state. A logic/select circuit couples the fuse bank to the number of multiplexors such that the state of the fuse determines the coupling between the number of local input/output lines to the number of global input/output lines. A system bus communicatively couples the central processing unit and the random access memory.
Thus, an improved redundant input/outline repair scheme is provided. The repair scheme selectively couples redundant elements into an integrated circuit. The r
Micro)n Technology, Inc.
Nelms David
Scgwegman, Lundberg, Woessner & Kluth, P.A.
Tran M.
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