Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1994-08-16
1995-08-15
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Data refresh
36523003, G11C 700
Patent
active
054425883
ABSTRACT:
Memory circuitry 200 is provided which includes first and second banks of memory cells 201 arranged in rows and columns. A first row decoder 210a is provided for selecting a row in the first bank 201a in response to a row address from a first group of row addresses. A second row decoder 210b is provided for selecting a row in the second bank 201b in response to a row address from a second group of row addresses. Row address circuitry 208/209 is provided for presenting a sequence of row addresses to the row decoders 210 in response to a single row address received at an address port to the memory circuitry 200, the row address circuitry 208/209 presenting only row addresses of the first group in a refresh mode. Refresh circuitry 217 couples the row address circuitry 208/209 with the second row decoder 210b, and in the refresh mode converts a row address in the first group presented by the row address circuitry 208/209 into a row address in the second group for use by the second row decoder 210b.
REFERENCES:
patent: 4570242 (1986-02-01), Nagami
patent: 4608666 (1986-08-01), Uchida
patent: 5251178 (1993-10-01), Childers
patent: 5329490 (1994-07-01), Murotani
patent: 5373475 (1994-12-01), Nagase
Cirrus Logic Inc.
Nguyen Tan
Popek Joseph A.
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