Circuits and methods for providing page mode operation in...

Details Circuits and methods for providing page mode operation in... Circuits and methods for providing page mode operation in...

2003-08-13

2004-11-30

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Byte or page addressing

C365S189070, C365S191000

Reexamination Certificate

active

06826115

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to Korean Patent Application No. 2002-61042, filed Oct. 7, 2002 in the Korean Intellectual Property Office, which is incorporated herein by reference.
TECHNICAL FIELD OF THE INVENTION
The present invention relates to circuits and methods for providing page mode operation in a semiconductor memory device having a partial activation architecture.
BACKGROUND
There is a continual demand for semiconductor devices such as DRAM (dynamic random access memory) devices, which provide fast and efficient memory access operations (read and write operations). But as the memory access speed of a DRAM increases, the power dissipation generally increases, which can pose serious problems. Therefore, when developing a semiconductor memory device, the operating speed and power dissipation is a trade-off relationship that is typically considered. Some techniques for controlling power dissipation while providing high-speed operation have focused on reducing the memory cell array currents. By way of example, semiconductor memory devices having a partial activation architecture have been developed, which enables one of a plurality of memory cell array blocks to be activated for performing a memory access operation in an activated memory block. One example of a semiconductor device having a partial activation structure is a FCRAM (fast cycle random access memory), which was developed by Fujitsu Ltd.
FIGS. 1A through 1C
illustrate a hierarchical memory architecture of a semiconductor memory device according to the prior art, which enables partial activation of blocks of memory cells. As shown in
FIG. 1A
, a semiconductor memory device (
10
) includes a plurality of memory banks (
10
A,
10
B,
10
C,
10
D). Each memory bank represents, for example, a logical unit of memory in a PC, and each bank may consist of one or more memory modules (e.g., DIMM (Dual In-line Memory Module), SIMM (Single In-Line Memory Module)). Each memory bank (
10
A,
10
B,
10
C,
10
D) is further logically divided into a plurality of memory cell array blocks. For instance, as depicted in the exemplary embodiment of
FIG. 1B
, the memory bank (
10
A) comprises four memory cell array blocks (
100
a,
100
b,
100
c,
100
d
).
In addition, each memory cell array block (
100
a,
100
b,
100
c,
100
d
) is further logically divided into a plurality of sub-memory cell array blocks (or column blocks), wherein each sub-memory cell array block is controlled by associated control circuitry. For instance, as depicted in the exemplary embodiment of
FIG. 1C
, the memory cell array block (
100
a
) comprises four sub-memory cell array blocks (
101
,
102
,
103
,
104
). The memory cell array block (
100
a
) further comprises a plurality of sub-wordline drivers (
105
,
106
,
107
,
108
), wherein each sub-wordline driver is associated with one of the sub-memory cell array blocks (
101
,
102
,
103
,
104
).
Each sub-wordline driver (
105
,
106
,
107
and
108
) activates a corresponding sub-wordline (WL
1
, WL
2
, WL
3
, WL
4
) of the corresponding column block. More specifically, wordlines of memory block (
100
a
) are formed over the memory block (
100
a
) using a global wordline framework, and such wordlines are activated by a row decoder based on an input row address (wordline address). The sub-wordlines are formed over corresponding column blocks and the sub-wordline drivers (
105
,
106
,
107
,
108
) control activation of corresponding sub-wordlines. For example, in the exemplary embodiment of
FIG. 1C
, when a row address and a column block selection address are input to the memory device, a global wordline corresponding to the input row address is activated by a row decoder. Furthermore, the input column block selection address is used to activate one of the column blocks (
101
,
102
,
103
,
104
), which causes a corresponding sub-wordline driver (
105
,
106
,
107
,
108
) to activate a corresponding sub-wordline having the same address as the activated (global) wordline.
The memory framework depicted in
FIGS. 1A-C
is one example of a memory framework that can be used for providing a partial activation semiconductor memory device, such as an FCRAM, whereby one of the sub-memory cell array blocks (
101
,
102
,
103
,
104
) can be activated using, for example, a column block address (CBA) to perform data access or refresh operations. For instance, in the exemplary embodiment of FIG.
1
C, since the memory cell array block (
100
a
) comprises four sub-memory blocks (
101
,
102
,
103
,
104
), a two-bit CBA can be used to select one of the four column blocks (sub-memory blocks), although one of ordinary skill in the art readily will appreciate that the memory framework can be designed with more or less column blocks that are individually addressable by predetermined column block selection addresses.
To perform a memory access operation using the memory framework shown in
FIGS. 1A-1C
, one of the memory banks (
10
A,
10
B,
10
C,
10
D) is initially selected in response to a predetermined bank address, and then a memory cell array block (
100
a,
100
b,
100
c,
100
d
) within the selected memory bank is selected in response to a predetermined address (e.g., row address or any other address depending on the addressing scheme). Then, a row address (RA) and column block selection address (CBA) are input to activate a global wordline (based on the decoding results of the input row address of the row decoder) and to activate a column block of the selected memory cell array block (based on the input CBA). Then, only the sub-wordline of the selected column block is activated (having the same address as the activated global wordline) by the corresponding sub-wordline driver.
For example, in the exemplary embodiment of
FIG. 1C
, when a column block selection address
00
is input, a sub-wordline WL
1
corresponding to the first column block (
101
) is activated based on the input row address. When the column block selection address
01
is input, a sub-wordline WL
2
corresponding to the second column block (
102
) is activated. When the column block selection address
10
is input, a sub-wordline WL
3
corresponding to the third column block (
103
) is activated. When the column block selection address
11
is input, a sub-wordline WL
4
corresponding to the fourth column block (
104
) is activated. Thus, only one-quarter of the memory cells having the same row address are activated. The data is then input/output to/from the activated column block depending on the input column line address(es). In addition, the sub-wordline of the activated column block is automatically inactivated, i.e., precharged, after a predetermined amount of time.
A FCRAM implements a partial activation mode to reduce current dissipation and to improve access speed. In a FCRAM, the tRAC (active restore time) and tRC (row precharge time) are 22 ns and 25 ns, respectively, which represents improvements for tRAC and tRC by 10% and 50%, respectively, as compared to conventional DRAMs.
There are some problems associated with operating a DRAM device in a partial activation mode as compared to a conventional DRAM. For example, it is difficult to perform a “page mode” operation for reading/writing data in a DRAM operating in a partial activation mode. As in known in the art, “page mode” generally denotes an operation mode in which data is input/output to/from a plurality of memory cells having the same row address X by changing only a column address Y, after the row address X is input once. Conventional DRAM devices operate in a “page mode” to provide increased memory access speed, while providing a reduction in the power consumption.
A page mode operation is difficult to implement in a DRAM that operates in a partial activation mode, because, as discussed above with reference to
FIG. 1C
, the memory cells connected to the same row address (global wordline address) are selectively activated/controlled based on the column block selection address, which is input with the row address. Mor

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