Circuits and methods for level shifting a signal

Details Circuits and methods for level shifting a signal Circuits and methods for level shifting a signal

2011-03-29

2011-03-29

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S068000, C326S093000, C326S083000

Reexamination Certificate

active

07915921

ABSTRACT:
In one embodiment, the present disclosure includes a level shift circuit. The level shift circuit includes a clocked latch to receive a digital data signal and a complement of the digital data signal. Outputs of the clocked latch are coupled to inputs of a second latch through capacitors. The clocked latch is powered by first and second power supply voltages that are different than third and fourth power supply voltages used for powering the second latch. Latch output signals from the second latch have high and low voltage values at the third and fourth power supply voltages. In one embodiment, transistors in circuitry driven by the level shift circuit may receive output signals from the level shift circuit that have high and low voltage values within a safe operating range of the transistor receiving the output signal.

REFERENCES:
patent: 7511554 (2009-03-01), Kaneko et al.
patent: 7564263 (2009-07-01), Walker et al.
patent: 7659754 (2010-02-01), Thiele et al.
patent: 2006/0197554 (2006-09-01), Jinta

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