Circuits and methods for initializing memory cells

Details Circuits and methods for initializing memory cells Circuits and methods for initializing memory cells

2001-12-10

2003-02-11

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000

Reexamination Certificate

active

06519177

ABSTRACT:

BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to the field of initializing memory. In particular, the present invention relates to circuits and methods for initializing the memory cells of a random access memory array to specified values.
2. Background and Related Art
Random access memory cells are used in a variety of computing products including personal computers and field programmable gate arrays. Random access memory cells are beneficial in such devices because data stored in the memory cells is easily overwritten and updated when the operating conditions of a device change or need to change.
Typically, random access memory is arranged as an array of memory cells that include multiple columns of memory cells. Writes to a random access memory cell are accomplished through one or more write ports or one or more read/write ports. A write or read/write port may use either singled ended or differential signaling.
In single ended signaling, a specified binary value is written to a random access memory cell by asserting the specified binary value on a single bit line attached to the write port of the memory cell. When the memory cell is write enabled, data on the single bit line is written into the memory cell. For instance if the value on the attached bit line is a binary zero when the memory cell is write enabled, a binary zero will be written into the memory cell.
In differential ended signaling, a write occurs in a random access memory cell using two bit lines. One bit line, designated as the “true” bit line, is coupled to one side of the memory cell and is driven to the logic value that will be written to the memory cell. The other bit line, designated as the “inverted” bit line, is coupled to the other side of the memory cell and is driven to a logic value that is opposite of the logic value to be written to the memory cell. Transistors are typically used in this type of memory cell. A write is accomplished by overdriving one or both sides of the memory cell through write enable logic thus causing the true and inverted sides of the memory cell to assume the logic levels asserted on the true and inverted bit lines. This results in the value carried on the true bit line being stored in the memory cell.
When using one or more columns of memory, a separate bit line or separate bit lines may be used for each column in the array. Each memory cell in a column may be coupled to the bit line or bit lines associated with the column, from which the memory cell may read and write data. Addressing logic is used to put individual memory cells in a state to read a value from or write a value to an associated bit line or differential pair.
When using random access memory, there are instances when it is beneficial to initialize all the memory cells of a memory array to predetermined values. For instance, part of the production process of random access memory cells involves testing the memory cells to see if they correctly store data. Each memory cell in a memory array must be able to correctly store a binary zero and a binary one. One approach is to sequentially write one binary value to the cells of a memory array a word at a time, read the values back to verify they are correct, then sequentially write the opposite binary value to the same memory cells a word at a time and read back the values to verify they are correct.
Another example of such testing is to write random bit patterns to a memory array. This is often done by writing a random pattern of zeroes and ones to the memory array, and then reading back the values stored each memory cell of the array to see if the values were stored correctly. Next, the inverse of the initial pattern is written to the memory array and each memory cell is again read to see if it stored the correct value. Using both sequentially writes and random bit patterns are time consuming because multiple write operations must be performed to test an array of memory.
As a result, other initialization methods, which reduce the time required to write values to the memory cells of a memory array, have been developed. One method is to add additional transistors to each memory cell. The additional transistors function to initialize each memory cell to a predetermined value upon power up. Thus, binary values are stored in all memory cells simultaneously. This increases the efficiency of the testing process by reducing the number of write operations. However, adding transistors to the memory cells of a memory array may increase the size of the memory array by more than 20% over the size of a similar array that does not include additional transistors.
Therefore, what are desired are circuits and methods for efficiently initializing a random access memory cells in a manner that does not require substantially increasing the size of associated memory arrays.
SUMMARY OF THE INVENTION
In accordance with the present invention, what are described are the structure and operation of a circuit that initializes the cells of a random access memory array. The circuit initializes all memory cells substantially simultaneously but does not substantially increase the overall size of the memory array. In one embodiment, the initialization circuitry does not affect the normal read and write operations of the memory array.
The memory initialization circuit includes an initialization input line, duplicated bit lines, and logic components. In the case of a memory array, which employs single ended memory cells, each memory cell is associated with a single bit line. In the case of a memory array, which includes multiple columns, a single bit line may serve a column of memory cells. In accordance with the present invention, instead of the single bit line, there are two bit lines associated with the column of memory cells even though single ended signaling is employed. Both of the bit lines run the length of the column of memory cells. At the time of manufacture each memory cell is coupled to one of the bit lines.
In the case of memory cells using differential signaling, each memory cell is associated with two bit lines. One is designated as the true bit -line and the other is designated as the inverted bit line. The binary value asserted on the true bit line is considered to be the logic value of the differential pair. In the present invention, both the true bit line and the inverted bit line are duplicated. One differential pair includes one of the true bit lines and one of the inverted bit lines, and the other differential pair includes the other true bit line and the other inverted bit line. This results in four bit lines being available to each memory cell. Included logic components may be used to address all memory cells simultaneously and may be used to force one differential pair to one logic value and the other differential pair to an opposite binary value. At the time of manufacture, each memory cell is coupled to either one or the other differential pair.
In operation, since each memory cell is coupled to only one bit line or to only one differential pair at the time of manufacture, and since each duplicated bit line or differential pair carries an opposite value, the memory cells of a memory array may be initialized to a predetermined pattern. After initialization, that is once the signal indicative of initialization is no longer carried on the initialization input, each duplicated bit line and each differential pair carries an identical value. Thus, after initialization, write operations occur as they would without duplication of any bit lines.
If a memory array using single ended memory cells is configured in columns, conventionally one bit line is used for each column. In this case, the bit line associated with each column would be duplicated and each memory cell in a column coupled to one or the other of the duplicated bit lines. During memory initialization one bit line for each column is forced to a logic zero and the other is forced to a logic one. Memory cells that are to be initialized to a logic zero are coupled at the time of man

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