Circuits and methods for generating internal signals for integra

Details Circuits and methods for generating internal signals for integra Circuits and methods for generating internal signals for integra

1999-09-15

2000-09-19

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Sync/clocking

3652335, 36523006, 365194, 327261, G11C 700, G11C 800

Patent

active

061222208

ABSTRACT:
Internal signals for integrated circuits are generated by a reset circuit that is responsive to an input signal to generate a reset signal pulse a predetermined time after the input signal is activated, and a dynamic inversion circuit that inverts the input signal in the absence of the reset signal pulse and that assumes an inactive state in response to the reset signal pulse, to thereby produce an output pulse that is activated by the input signal and that is deactivated by the reset circuit as a function of the predetermined time. Methods of operating integrated circuits generate a reset signal pulse a predetermined time after an input signal is activated. The input signal is inverted until the reset pulse is generated, to thereby produce an output pulse that is activated by the input signal and that is deactivated by the reset circuit as a function of the predetermined time. Accordingly, circuits and methods for generating internal clock signals for integrated circuits by dynamic inversion and resetting can rapidly generate internal clock signals from external clock signals and can have reduced susceptibility to noise.

REFERENCES:
patent: 5813023 (1998-09-01), McLaury
patent: 5815462 (1998-09-01), Konishi et al.
patent: 5892730 (1999-04-01), Sato et al.
patent: 5923613 (1999-07-01), Tien et al.
patent: 5946244 (1999-08-01), Manning
patent: 5995441 (1999-11-01), Kato et al.
patent: 6026045 (2000-02-01), Son
patent: 6044023 (2000-03-01), Proebsting

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