Circuits and methods for debugging an embedded processor and...

Details Circuits and methods for debugging an embedded processor and... Circuits and methods for debugging an embedded processor and...

2005-09-20

2005-09-20

Beausoliel, Robert (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S030000, C714S047300

Reexamination Certificate

active

06948098

ABSTRACT:
A debugging subsystem for testing a system-on-a-chip includes an embedded processor and memory and includes at least one debugging subblock monitors a bus between the processor and the memory to detect selected triggering events, counts the number of triggering events detected and when the number of triggering events reaches a predetermined threshold, generates a debugging signal.

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Bannatyne, Ross, “Debugging Aids for Systems-on-a-Chip”, IEEE, 1998.

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