Electronic digital logic circuitry – Exclusive function – With field-effect transistor
Reexamination Certificate
2002-03-28
2004-04-20
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Exclusive function
With field-effect transistor
C326S044000, C327S199000
Reexamination Certificate
active
06724221
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to logic functions and latches in electronic circuitry, and more particularly to such functions and latches which are suitable for application with a high frequency clock.
2. Related Art
Numerous electronic circuits applications require exclusive-OR (“XOR”) logic interconnected with storage elements, such as latches. For example, fundamental elements of CMOS serial communications links, such as phase detectors, often have exclusive-OR gates connected to latches of flip flops. In another example, built in self test circuitry generally requires exclusive-OR gates in a linear feedback shift register block, in order to automatically generate test patterns. In yet another example, arithmetic blocks often require exclusive-OR functionality that ends in some sort of latch-based storage. As computer systems operate at higher and higher clock speeds there is an increasing need for faster and faster circuitry, including circuitry having the above described exclusive-OR logic functionality output to a latch.
SUMMARY
The foregoing need is addressed in the present invention. In one form of the invention, circuitry having exclusive-OR and latch functionality includes timing circuitry and logic circuitry. The circuitry includes a memory, with first and second memory nodes, for storing a state and its complement, and first and second timing circuitry portions, each operable to receive at least one timing signal, coupled to the respective memory nodes. The logic circuitry includes first and second logic circuitry portions, each of which is operable to receive at least first and second data signals. Each logic circuitry portion has a conditionally conducting path, coupled in series with a conditionally conductive path of one of the respective first and second timing circuitry portions, for controlling pulling up and pulling down the respective memory nodes responsive to the following conditions: i) the first data signal being asserted and the second data signal being de asserted and ii) the first data signal being de asserted and the second data signal being asserted.
In another aspect, the first timing circuitry portion has first pull up and pulldown sections, and the second timing circuitry portion has second pull up and pulldown sections. The logic circuitry portions are coupled in series with respective ones of the timing circuitry portions.
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Boerstler David William
Burns Jeffrey L.
Carballo Juan-Antonio
Nowka Kevin John
Shi Li
Cho James
England Anthony V. S.
International Business Machines - Corporation
Salys Casimer K.
Tokar Michael
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