Circuitry for rounding in a floating point multiplier

Details Circuitry for rounding in a floating point multiplier Circuitry for rounding in a floating point multiplier

1991-05-03

1992-09-22

Malzahn, David H.

Boots, shoes, and leggings

364748, G06F 752

Patent

active

051503190

ABSTRACT:
A rounding circuit for a binary tree floating point multiplier including apparatus for providing the upper bits of a mantissa presuming that no carry-in has occurred without waiting for the generation of a carry-in from lower order bits, apparatus for providing the upper bits of a mantissa presuming that a carry-in has occurred without waiting for the generation of a carry-in from lower order bits; apparatus for providing a first set of lower order bits for the mantissa based on an actual carry-in from a lower order bit adder and a rounding condition, the first set of lower order bits for the mantissa being chose for no mantissa overflow; apparatus for providing a second set of lower order bits for the mantissa based on an actual carry-in from a lower order bit adder and a rounding condition, the second set of lower order bits for the mantissa being chosen for mantissa overflow; and apparatus for selecting upper order bits and lower order bits for the mantissa based on whether a carry-in propagates past the lower order bits of the mantissa and whether a mantissa overflow has occurred.

REFERENCES:
patent: 4926370 (1990-05-01), Brown et al.
patent: 4941120 (1990-07-01), Brown et al.
patent: 4977535 (1990-12-01), Birger
patent: 5027308 (1991-06-01), Sit et al.

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