Circuitry cross-talk analysis with consideration of signal...

Details Circuitry cross-talk analysis with consideration of signal... Circuitry cross-talk analysis with consideration of signal...

2005-09-27

2005-09-27

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06950999

ABSTRACT:
A method for evaluating cross-talk of a circuit and signal degrading due to mutual electric coupling between wires of a circuit. The method includes: simulating the signal transmitting on wires of the circuit during the normal operation of the circuit, and implementing cross-talk analysis of the circuit to modify the analysis according to the signal variation during the practical operation of the circuit in order to evaluate the cross talk on each wire in the circuit.

REFERENCES:
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patent: 5596506 (1997-01-01), Petschauer et al.
patent: 6721930 (2004-04-01), Sasaki et al.
patent: 6772403 (2004-08-01), Sasaki
patent: 2002092069 (2002-03-01), None
patent: WO 01/82145 (2001-11-01), None
Sicard et al., “Cross-Talk Extraction from Mask Layout”, Feb. 1993, IEEE Proceedings, 4thEuropean Conference on Design Automation, pp. 414-418.
Sasaki et al., “Multi-agressor Relative Window Method for Timing Analysis Including Crosstalk Delay Degradation”, May 2000, IProceeding of the IEEE 2000 Custom Integrated Circuits Conference, pp. 495-498.
Sasaki et al., “Building a Crosstalk Library for Relative Window Methods-Timing Analysis that Includes Crosstalk Delay Degradation”, Aug. 2000, IEEE, Proceeding of the second IEEE Asia Pacific Conference on ASICs, pp. 371-374.

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