Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-05-22
2002-01-01
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S040000, C326S039000, C326S038000
Reexamination Certificate
active
06335634
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to programmable logic devices (“PLDs”), and more particularly, to circuitry for interconnecting and driving signals onto various programmable logic device interconnects.
Programmable logic devices are well known as is shown, for example, by Pedersen et al. U.S. Pat. No. 5,260,610 and Cliff et al. U.S. Pat. No. 5,260,611.
There is continued interest in programmable logic devices with greater logic capacity. This calls for devices with larger numbers of regions of programmable logic. It also calls for logic devices with greater programmable interconnectivity for making needed connections between the increased numbers of logic regions. It is important, however, to organize interconnection resources judiciously so that those resources provide flexible interconnectivity, but do not begin to take up excessive amounts of space on the device, thereby unduly interfering with the amount of additional logic that can be included in the device. To accomplish this, it would be desirable to find ways to organize the interconnection resources on programmable logic devices so that the efficiency of utilization of the interconnection resources can be maximized. More interconnectivity could therefore be provided in the device to serve more logic in the device without simply adding more interconnection resources with the increased logic capability.
It is therefore an object of this invention to provide improved arrangements of interconnection resources for programmable logic devices.
It also an object of the invention to provide programmable logic device interconnection arrangements that can efficiently and flexibly interconnect larger numbers of programmable logic regions than previously possible.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the present invention by providing arrangements for interconnecting resources on programmable logic devices that have a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Each logic super-region in such a programmable logic device includes a plurality of regions of programmable logic and a plurality of inter-region interconnection conductors associated with the regions for conveying signals to and between the regions in that super-region. Each region may include a plurality of subregions of programmable logic. A typical subregion is programmable to perform any of several logical operations on a plurality of input signals applied to the subregion to produce an output signal of the subregion. Programmable logic connectors and local conductors may be associated with the regions for selectively bringing signals from the associated inter-region conductors to the subregions in that region for use as inputs. Interconnection groups may be used to selectively apply subregion output signals to the associated inter-region conductors.
A plurality of horizontal inter-super-region interconnection conductors may be associated with each row of super-regions for selectively conveying signals to, from, and between the super-regions in the that row. Similarly, a plurality of vertical inter-super-region interconnection conductors may be associated with each column of super-regions for selectively conveying signals to, from, and between the super-regions in that column.
The local conductors for selectively bringing signals into the region may include region-feeding conductors for bringing signals into the programmable logic region and local feedback conductors for making output signals of the region available as inputs to the region (i.e. recirculating signals in a programmable logic region). The region-feeding conductors are programmably connectable to the inter-region interconnection conductors. The region feeding conductors convey signals from the inter-region interconnection conductors to the inputs of the subregions in the region. The local feedback conductors are programmably connectable to the input of the subregions. The local feedback conductors supply feedback signals from the subregions to the inputs of the subregions.
Programmable interconnection groups may be used for various interconnection tasks such as turning signals traveling on inter-super-region and inter-region conductors onto other conductors and applying subregion output signals to the inter-super-region and inter-region conductors. The interconnection groups are typically organized so that they selectively direct signals from logic regions and inter-region and inter-super-region conductors to other inter-region and inter-super-region conductors.
Each interconnection group preferably has a number of programmable multiplexers (switching circuits). In one suitable arrangement, a programmable multiplexer in an interconnection group may select as an output signal: (1) one or more output signals from an associated logic region, (2) one or more output signals of an adjacent logic region, or (3) one or more inter-region or inter-super-region conductor signals. The interconnection group may apply the selected signal to a driver circuit. Output signals from the driver circuit may be programmably connected (e.g., using a demultiplexer or second multiplexer) to one or more inter-region or inter-super-region conductors. This arrangement provides a number of pathways for routing signals from logic elements and conductors to each conductor type. This arrangement also helps to reduce the amount of interconnection circuitry on the programmable logic device by reducing or eliminating the need for numerous dedicated interconnection circuits.
Some of the programmable interconnection groups, such as those near the periphery of the device, may also receive signals from input/output (“I/O”) pins. These interconnection groups may be used to route signals from the I/O pins to the appropriate conductors on the device. Some I/O pins may have dedicated interconnection groups that route signals to one or more inter-super-region conductors and/or one or more inter-region interconnection conductors.
The region-feeding conductors and local feedback conductors are generally not directly connected to the inter-super-region conductors. In order to reach a local or region-feeding conductor, signals from inter-super-region conductors must be routed through an interconnection group and inter-region interconnection conductors. This arrangement reduces the number of programmable connections used to connect signals to the local and region-feeding conductots.
The interconnection groups increase interconnectivity and routing flexibility on the programmable logic device without using excessive amounts of interconnection resources. The interconnection groups also help to minimize the number of blocked signal routes encountered when implementing a design on the programmable logic device. Interconnections groups may reduce the area required for a programmable logic device with a given amount of logic circuitry by reducing the number of programmable interconnections that are needed on the device. The interconnection groups may also help to reduce the number of interconnection conductors used in routing various signals, thereby reducing parasitic loading and increasing the speed of the device.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
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pate
Cliff Richard G.
Lane Christopher F.
Lee Andy L.
McClintock Cameron R.
Mejia Manuel
Tan Vibol
Tokar Michael
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