Circuitry and methodology to establish correlation between...

Details Circuitry and methodology to establish correlation between... Circuitry and methodology to establish correlation between...

2007-11-20

2007-11-20

Nguyen, Vinh (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010

Reexamination Certificate

active

11088953

ABSTRACT:
A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area. A preferred methodology, more specifically, is as follows: (1) Test structures at start both in parallel stress mode and in ring oscillator or “product” mode; (2) Analyze the breakdown data as per the present state of the art for each of the areas based on the parallel stress mode; (3) Combine the above breakdown distributions using the area scaling to improve the confidence bounds of the Weibull slope of the cumulative distribution function; (4) Test the ring oscillators in the product mode to determine how many of the stress fails are also product fails as defined by an operational degradation; (5) Subdivide the failures to determine the relationship between the first fail, and the second fail, and the nth fail; (6) Investigate which stress fail, if not the first stress fail, is more likely to cause a product fail as defined by operational degradation; and (7) Based on the subdivision in step 5 and the results in step 6, make projection based on that fail which is most likely to cause fail. The methodology as outlined above bridges between dielectric stress fails and product degradation both in the case of each stress fail causing a product degradation, as well as in the case where more than one stress fail occurs before any product degradation occurs. And this relationship can be quantified.

REFERENCES:
patent: 3796955 (1974-03-01), Bhattacharyya et al.
patent: 5619462 (1997-04-01), McClure
patent: 5625288 (1997-04-01), Snyder et al.
patent: 5898706 (1999-04-01), Defresne et al.
patent: 5900644 (1999-05-01), Ying et al.
patent: 6049213 (2000-04-01), Abadeer
patent: 6060791 (2000-05-01), Goerz et al.
patent: 6133746 (2000-10-01), Fang et al.
patent: 6181154 (2001-01-01), Beffa
patent: 6628134 (2003-09-01), Lee
patent: 6657241 (2003-12-01), Rouse et al.
patent: 6724214 (2004-04-01), Manna et al.
Electrical Breakdowns and Breakdown Mechanism in Ultrathin Silicon Oxides, J.C. Jackson, et al., Microelectronics Reliability 39 (1999) pp. 171-179.
Defensive Publication T944, 007, Testing Systems and Processes for Manufacturing Complex Articles, R.M. Booth, Jr., et al. Mar. 2, 1976.
Gate Quality Tests at Polysilicon Etch Step on CMOS Products, IBM Technical Disclosure Bulletin, vol. 32, No. 3B, Aug. 1989.

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