Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-06-16
2008-12-02
Ellis, Kevin (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07461208
ABSTRACT:
A circuit for accessing an associative cache is provided. The circuit includes data selection circuitry and an outcome parallel processing circuit both in communication with the associative cache. The outcome parallel processing circuit is configured to determine whether an accessing of data from the associative cache is one of a cache hit, a cache miss, or a cache mispredict. The circuit further includes a memory in communication with the data selection circuitry and the outcome parallel processing circuit. The memory is configured to store a bank select table, whereby the bank select table is configured to include entries that define a selection of one of a plurality of banks of the associative cache from which to output data. Methods for accessing the associative cache are also described.
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Handy, Jim., “The Cache Memory Book,” 1998, Academic Press Limited, 2nd Edition, ISBN: 0-12-322980-4, pp. 16 & 62.
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Caprioli Paul
Chaudhry Shailender
Yip Sherman H.
Eland Shawn
Ellis Kevin
Martine & Penilla & Gencarella LLP
Sun Microsystems Inc.
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