Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2007-10-04
2010-11-09
Puente, Eva Y (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S326000, C375S320000, C375S356000, C331S016000, C331S017000, C331S025000
Reexamination Certificate
active
07831007
ABSTRACT:
Described is circuitry for improving the acquisition/locking time of phase-locked loops (PLL). The circuitry includes a node for tapping voltage from a PLL, with an analog-to-digital converter (ADC) to convert the voltage to a digital signal. A memory module stores the digital signal. A digital-to-analog converter (DAC) converts the digital signal to an analog output. A comparator/threshold detector is included to compare the voltage from the node to the analog signal from the DAC. Based on the comparison, the comparator/threshold detector provides a signal to the memory module to cause the memory module to update its stored digital signal. Upon power-up, the saved voltage is forced into the PLL to force the PLL nodes to the saved values as an initial condition, thereby decreasing acquisition time in the phased locked loop.
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HRL Laboratories LLC
Puente Eva Y
Tope-McKay & Assoc.
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