Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
1999-12-08
2001-06-12
Graybill, David E. (Department: 2814)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
C438S599000, C438S613000, C438S666000
Reexamination Certificate
active
06245599
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an automatic wiring in designing a substrate of a circuit wiring system of semi-conductor package substrates, for example, a ball grid array (BGA) package or chip scale package (CSP), and quality rating of a wiring route.
BACKGROUND OF THE INVENTION
In designing a substrate for a ball grid array (BGA) package or a chip scale package (CSP) which is hailed as the mainstream of a future LSI (large-scale integrated circuit) packaging system designed for high-density packaging, it will become necessary to improve quality of wiring routes by improving the efficiency of wiring route design, and at the same time, performing the inspection on the conformity to wiring rules. Furthermore, a technology valid for automatic wiring in substrate designing, which rates based on the quality standard for rating quality of wiring routes through introduction of a rating function will be required.
For a BGA substrate shown as one example in
FIG. 4
, solder ball connection pads
2
are arranged in the center of the BGA substrate, and wire bond pads
5
are arranged around the outside circumference of the solder ball connection pads
2
.
Now, let us assume that, in the above BGA substrate, the solder ball connection pads
2
and wire bond pads
5
are connected as shown in FIG.
4
. In this case, under such design condition that the wire bond pads
5
can be connected to any of the solder ball connection pads
2
(free connection), there are many combinations of the wire bond pads
5
and solder ball connection pads
2
, therefore it took time in determining the wiring route.
The Print Circuit Board Wiring Method, the Japanese Patent Examination SH058-112383, disclosed the method of generating candidates for possible wiring routes based on the connection relationship between the pre-designated wire bond pads and solder ball connection pads, and selecting the wiring route by considering wiring length, and so on.
Another technique disclosed in the Japanese Patent Examination HEI05-67178 is designed to improve wiring processing at higher speed and the wiring performance. The conventional technique is an automatic wiring processing method characterized by estimating the conjestion of wiring on the substrate, setting the area for separating the substrate larger than the specified value when the wiring conjestion is higher than the specified value so that the wiring can be easily succeeded, and setting the area for separating the substrate smaller than the specified value when the wiring conjestion is smaller than the specified value so that the time for wiring processing can be minimized, and by completing the wiring on the entire substrate by wiring for each area having different size. In this conventional technique, after inputting the input-side pin, output-side pin, and the wiring information between the pins on the input side and the output side, and disclosed the method of wiring processing the wiring result satisfied the wiring rule at high speed.
With regard to the improvement of the automatic wiring ratio by uniforming wiring conjestion, there is a technique disclosed in Japanese Patent Examination HEI06-45443. This conventional technique is about the layered wiring method in which a reflexive division of a wiring area is repeated, and in each divided layer, in an automatic wiring method of semiconductor integrated circuit which determines the route passing position of a set (hereinafter called the net) of circuit pins (hereinafter called the pins) of a same electric potential on the division line by using an optimization algorithm, the wiring area is divided into four parts by vertically and horizontally at the same time, and determines the passing position of the route of the net on the four division lines. In this leyered wiring method, after the pins on the input side, the pins on the output side, and the wiring information between the pins on the input side and the output side are input, when a cirtuit drawing is made to a wiring substrate drawing, a finalized wiring information is laid out into the wiring substrate drawing, the division of the wiring area into four parts is reflectively repeated so that the wiring substrate is subdivided by 4×m, and the route pattern on the area divided into four parts, and the net passing position on the four division lines are determined and the wiring route decision for route optimization (the shortest route determination) is automatically designed.
The conventional art relates to the method of drawing a substrate diagram by automatically designing the wiring route which performs the optimization of the writing route, where the input pin information targeted for connection and the output pin information targeted for connection, and the circuit information such as wiring rules or wiring limitation are already known. Therefore, the conventional art is limited to solving the wiring route optimization problems on the plane, such as the intersection of the wiring routes, overlapping the wiring routes, or the existence of an obstacle area which is forced to detour by the wiring routes.
In this way, in the conventional determination method of wiring routes, the combination of connecting the wire bond pads and solder ball connection pads had to be determined beforehand. Furthermore, it also took much time in determining the candidates for the combination of connections. Therefore, the wiring route determination took a lot of time because there were lots of connection combinations in the method of connecting wiring routes freely without determining the combination of the above connections.
Therefore, in the conventional art, the combination of connecting the wire bond pads and solder ball connection pads had to be firstly made. For example, if the number of wire bond pads is assumed to be n and the number of solder ball connection pads to be m, then there are
m
C
n
units combinations when m>n. Selecting an optimal connection combination out of the
m
C
n
units combinations can be regarded as the wiring route optimization problem on the BGA or CSP.
As an example, suppose if an electrode on the semi-conductor chip is the input pin, and an electrode on the semi-conductor package substrate is the output pin, then it is to solve the problem of seeking a possible output pin as well as the possible maximum number of wiring routes on the semiconductor package substrate when only the input pin information is known.
To seek the solution of this problem, first of all, the possible maximum number of wiring routes is obtained, and then the number of output pins which can be connected to the wiring routes is obtained. Then, quality standard is set for the output pins, and the maximum and minimum values of the quality standard are obtained based on the rating function so as to obtain the wiring route determination method which performs optimization of the wiring routes.
As shown in
FIG. 4
, the wire bond pads
5
are arranged on the outside circumference of the solder ball connection pads
2
, and a case in which the wire bond pads
5
and the solder ball connection pads
2
are wired like a wiring
3
is considered. The wire bond pads
5
, under the design condition in which they can be connected to any solder ball connection pads
2
, which are connected to one wire bond pads
5
, there are combinations equivalent to the number of solder ball connection pads
2
, and furthermore, there is a plurality of wiring routes regarding the combination of one connection.
The prime objective of this invention is to automatically select a combination of connecting a plurality of first pins and a plurality of second pins, select an optimal route and to layout a wiring route.
Another objective of this invention is to offer a rating result based on which the optimal wiring route is selected by rating the laid out wiring route based on the quality standard.
SUMMARY OF THE INVENTION
A circuit wiring system may comprise a design condition memory for storing a layout information of a first pin area in which a plurality of first pin
Arita Takashi
Goto Akihiro
Kawaguchi Hirochika
Ookyuu Satoshi
Takahashi Takao
Burns Doane , Swecker, Mathis LLP
Graybill David E.
Mitsubishi Denki & Kabushiki Kaisha
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