Circuit wiring layout in semiconductor memory device

Details Circuit wiring layout in semiconductor memory device Circuit wiring layout in semiconductor memory device

2007-07-17

2007-07-17

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

C326S101000, C326S106000, C365S185230, C365S230060

Reexamination Certificate

active

11266544

ABSTRACT:
A circuit wiring layout in a semiconductor memory device comprises first and second p-type MOS transistors having channels connected to each other in series, and first and second n-type MOS transistors having sources connected in parallel to a drain of the second p-type MOS transistor, the p- and n-type MOS transistors forming a decoder NOR gating portion. The first and second n-type MOS transistors having drains connected to first and second main lines, respectively, and sources connected to a section line. The first and second p-type MOS transistors having gates to which select signals for first and second accesses are applied, respectively. The first and second p-type MOS transistors share an active junction with each other in a first area. The first and second n-type MOS transistors are spaced from the first area in a direction of the section line and have independent active junctions.

REFERENCES:
patent: 5295105 (1994-03-01), Atsumi
patent: 6084819 (2000-07-01), Kablanian
patent: 6352868 (2002-03-01), Yang
patent: 6741510 (2004-05-01), Ohbayashi et al.
patent: 2004/0218456 (2004-11-01), Choi

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