Circuit verification

Details Circuit verification Circuit verification

2006-04-11

2006-04-11

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07028279

ABSTRACT:
In one embodiment, a system for verifying a circuit using a scheduling technique includes one or more partitioned ordered binary decision diagram (POBDD) modules that collectively generate one or more POBDDs. Each POBDD corresponds to one or more partitions of a state space of the circuit and includes a number of states and a number of nodes in the partition. The system also includes one or more cost metrics modules that collectively determine a processing cost of each of the partitions of each of the POBDDs. The system also includes one or more scheduling modules that collectively schedule processing of the partitions of the POBDDs for semiformal verification of a circuit. The schedule is based, at least in part, on the determined processing costs of the partitions of the POBDDs.

REFERENCES:
patent: 6086626 (2000-07-01), Jain et al.
patent: 6292916 (2001-09-01), Abramovici et al.
patent: 6308299 (2001-10-01), Burch et al.
patent: 6321186 (2001-11-01), Yuan et al.
patent: 6473884 (2002-10-01), Ganai et al.
patent: 6499129 (2002-12-01), Srinivasan et al.
G. Cabodi, P. Camurati, S. Quer, “Improved Reachability Analysis of Large Finite State Machines,” IEEE ICCAD, 1996.

Affiliated with

Also associated with

Rating

Circuit verification does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit verification, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit verification will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3550171