Circuit to reduce power supply fluctuations in high...

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies

Reexamination Certificate

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Details

C713S400000, C713S401000, C713S500000, C713S502000, C713S503000, C713S600000, C713S601000

Reexamination Certificate

active

07350096

ABSTRACT:
The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is coupled to the output of the counter. A processor means is coupled to the output of the first divider, thereby lessening current surges.

REFERENCES:
patent: 4654851 (1987-03-01), Busby
patent: 5964881 (1999-10-01), Thor
patent: 6700421 (2004-03-01), Mirov et al.
patent: 6750693 (2004-06-01), Duewer
patent: 7000130 (2006-02-01), Adachi
patent: 2005/0198550 (2005-09-01), Ramsden
patent: 2006/0093047 (2006-05-01), Boerstler et al.

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