Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
1999-12-30
2002-04-23
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S098000, C326S093000
Reexamination Certificate
active
06377078
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of integrated circuits and, more specifically, to logic circuits designed for high-speed operation, such as domino logic circuits.
2. Description of the Related Art
Performance goals of processors increase with every generation, and progressively more sophisticated architectures are required to implement their complex functions. Advanced architectures require long pipelines operating at very high frequencies. These higher frequencies demand increased usage of sophisticated circuit design styles like domino circuits.
Domino circuits increase the speed performance of logic circuits by reducing the capacitance associated with the use of P-type metal oxide semiconductors (“MOS”). Domino circuits accomplish this by precharging a series of logic gates during a first clock phase, or precharge cycle, and evaluating the intended logic function during the next clock phase, or evaluation cycle. However, domino circuits tend to be susceptible to the problem of charge sharing between internal nodes. Domino circuits using pulsed clocks do not lend themselves to the standard intermediate node precharge methods. Internal nodes provide connecting points internal to the circuit and they do not provide output signals. The occurrence of charge sharing in a domino circuit may cause device failure.
FIG. 1
represents a prior art domino circuit
150
which is typically susceptible to the problem of charge sharing. Domino circuit
150
contains a P-type transistor P
1
170
, which is used for precharge, and two N-type transistors N
1
and N
2
172
, which perform a logic function. A third N-type transistor N
3
174
is used to perform an evaluation function.
During the precharge cycle, a precharge pulsed clock (“Pclk”)
160
transistions low and turns on transistor P
1
. When transistor P
1
is on and evaluation pulsed clock (“Eclk”)
166
is inactive, node A
180
is precharged. Node B stays low if input B
162
is low, which keeps transistor N
1
off. However, if input B
162
changes its logic state from low to high after the precharge cycle, it turns on transistor N
1
. When transistor N
1
is on, it connects node A
180
and node B
182
. Consequently, the charge stored at node A
180
would have to be shared with node B
182
since the charge stored at node B is lower than the change at node A. The occurrence of a charge sharing between node A and node B typically causes output
156
to be undefined. Accordingly, an undefined output value may cause device failure.
Therefore, it is desirable to have a mechanism that prevents or reduces the occurrence of charge sharing in a domino circuit that uses a pulsed clock.
SUMMARY OF THE INVENTION
A circuit includes at least one input, an evaluate pulsed clock, and an output. In one embodiment, the circuit precharges an intermediate node in the circuit in response to a precharge pulsed clock and the evaluate pulsed clock.
Additional features and benefits of the present invention will become apparent from the detailed description, figures and claims set forth below.
REFERENCES:
patent: 5642061 (1997-06-01), Gorny
patent: 5764089 (1998-06-01), Partovi et al.
patent: 5828234 (1998-10-01), Sprague
patent: 5838169 (1998-11-01), Schorn
patent: 5880608 (1999-03-01), Mehta et al.
patent: 6046606 (2000-04-01), Chu et al.
patent: 6052008 (2000-04-01), Chu et al.
patent: 6060910 (2000-05-01), Inui
patent: 6111434 (2000-08-01), Ciraula et al.
Patra, P.; Narayanan, U. Automated phase assignment for the synthesis of low power domino circuits. pp. 379-384, Jun. 1999.
Intel Corporation
Tan Vibol
Tokar Michael
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