Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Input noise margin enhancement
Reexamination Certificate
2008-01-01
2008-01-01
Barnie, Rexford (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Input noise margin enhancement
C326S021000, C326S030000, C326S031000
Reexamination Certificate
active
10778455
ABSTRACT:
A serial data receiver circuit includes a pair of differential input nodes, and receiver circuitry and a termination circuit coupled between the differential input nodes. The termination circuit comprises a common mode node. A common mode control circuit is connected to the common mode node, and exhibits a substantially zero output impedance. In so doing, the common mode control circuit provides a common mode voltage to the common mode node of the termination circuit that exhibits substantially ideal termination of common mode signals and negligible loading on the differential input nodes. In another aspect, selection circuitry is provided that selectively passes single-ended or differential test signals to the differential input nodes during a test mode of operation. The selection circuitry facilitates observation of signals within the receiver circuitry.
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Bhakta Bhavesh G.
Payne Robert Floyd
Simpson Richard
Barnie Rexford
Brady W. James
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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