Circuit technique to achieve power up tristate on a memory bus

Details Circuit technique to achieve power up tristate on a memory bus Circuit technique to achieve power up tristate on a memory bus

2005-12-08

2009-06-02

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Tri-state

C326S057000, C326S062000, C326S082000

Reexamination Certificate

active

07541835

ABSTRACT:
Techniques and circuits for ensuring undefined control signals are not inadvertently driven onto a bus due to core logic and I/O logic supply voltages reaching final voltage levels at different times are provided. According to some embodiments, an internal voltage supply sense circuit may monitor a level of a voltage supply that powers core logic that generates control signals to be driven on I/O pads. The sense circuit may generate one or more control signals used to keep I/O pads in a high impedance state.

REFERENCES:
patent: 6335637 (2002-01-01), Correale et al.
patent: 6744298 (2004-06-01), Yamauchi et al.
patent: 6753697 (2004-06-01), Nakase

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