Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2007-03-27
2007-03-27
Sough, Hyung (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S102000, C714S048000
Reexamination Certificate
active
10667481
ABSTRACT:
The present invention is a method, circuit and system for storing bits on a Non-Volatile Memory (“NVM”) array. According to some embodiments of the present invention, a bit scrambling block may rearrange the received block of bits according to a spreading pattern. An error correction code block may generate an error correction code (“ECC”) based on either the original block of bits or based on the rearranged block of bits, and a data storing circuit may store in the NVM array the ECC and the block of bits from which the ECC was not derived.
REFERENCES:
patent: 6175937 (2001-01-01), Norman et al.
patent: 2003/0135798 (2003-07-01), Katayama et al.
International Search Report PCT/IL04/00783.
Cohen Zeev
Marcu Alon
Raz Meirav
Eitan Law Group
Infineon Technologies Flash GmbH & Co. KG
Song Jasmine
Sough Hyung
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