Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Patent
1997-10-03
2000-05-02
Lintz, Paul R.
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
703 15, 39550036, G06F 1750
Patent
active
060567848
ABSTRACT:
The invented method addresses two important issues concerning don't cares in formal system or circuit synthesis verification. First, it is shown how to represent explicit don't cares in linear space in a flattened hierarchy. Many circuits need this information for verification, but the classical calculation can be exponential. Second, three interpretations of verification on incompletely specified circuits are explored and it is shown how the invented method makes it easy to test each interpretation. The invented method involves transforming each cell within an original circuit that implements an incompletely specified function into set of plural cells that implement the upper and lower bound of the interval of the function. The method thus constructs networks for the endpoints of the intervals and, rather than constructing traditional miters, connects the outputs of the interval circuits with the logic appropriate for the property, e.g. equality or consistency, that is to be verified. The invented apparatus includes operatively coupled processors, e.g. hardware, software or firmware processors, that cooperate to implement the invented method.
REFERENCES:
patent: 5745373 (1998-04-01), Watai et al.
patent: 5892687 (1999-04-01), Moricz et al.
Damiani, Maurizio and Giovanni DeMicheli "Don't Care Set Specifications in Combinational And Synchronous Logic Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12 No. 3, Mar. 1993.
Damiani, Maurizio "Nondeterministic Finite-State Machines And Sequential Don't Cares," IEEE, 1994.
Matsuda et al. "256Bit Parallel XOR Gate Operating With Optical Input and Output," IEEE, 1990.
Devadas et al. "Redundancies and Don't Cares in Sequential Logic Synthesis," 1989 International Test Conference, IEEE.
Zemva et al. "A Functionality Fault Model: Feasibility and Applications," IEEE, 1994.
Sucar, Hector R. "Comprehensive Structural Testing of ASIC Macrocells, a Comparative Analysis," Asic Conference and Exhibit, 1992 IEEE.
Yamada et al. "Process, Performance, and Reliability of Characterization of a GaAs VLSI Technology," IEEE, 1993.
D. Brand, "Verification of Large Synthesized Designs," Proc. 1993 IEEE Intl. Conf. on CAD, Nov. 1993, pp. 534-537.
D. Brand, R.A. Bergamaschi, and L. Stok, "Be Careful with Don't Cares," Proc. 1995 IEEE Intl. Conf. on CAD, Nov. 1995, pp. 83-86.
F.M. Brown, Boolean Reasoning, Kluwer Academic Publishers, Boston, 1990.
R.E. Bryant, "Graph-based Algorithms for Boolean Function Manipulation," IEEE Trans. Computers., vol. 35, No. 8, Aug. 1986, pp. 677-691.
R.E. Bryant, "On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication," IEEE Trans. Computers., vol. 40, No. 2, Feb. 1991, pp. 205-213.
E. Cerny, "An Approach to a Unified Methodology of Combinational Switching Circiuts," IEEE Trans. Computers., vol. 26, No. 8, Aug. 1977, pp. 745-756.
J. Jain, R. Mukherjee, and M. Fujita, "Advanced Verification Techniques Based on Learning," Proc. 32nd ACM/IEEE DAC, Jun. 1995, pp. 420-426.
W. Kunz, "Hannibal: An Efficient Tool for Logic Verification Based on Recursive Learning,"Proc. 1993 IEEE Intl. Conf. on CAD, Nov. 1993, pp. 538-543.
Y. Matsunaga, "An Efficient Equivalence Checker for Combinational Circuits," Proc. 33rd ACM/IEEE DAC, Jun. 1996, pp. 629-634.
D. Stoffel and W. Kunz, "Logic Equivalence Checking by Optimization Techniques," Proc. Intl. Workshop on CAD, Test and Evaluation for Dependability, Jul. 1996, pp. 85-90.
Garbowski Leigh Marie
Lintz Paul R.
Synopsys Inc.
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