Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-11-02
2001-11-06
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06314553
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to integrated circuit fabrication, and more particularly to a system and method for synthesizing and verifying a timed circuit based on a behavioral description.
BACKGROUND INFORMATION
The design of timing in digital circuits is an extremely difficult challenge. Conventional clocked digital design solves this problem by decomposing the circuit into cycle-free combinational logic (CL) stages and interstage clocked latches; the clock cycle is simply tuned to accommodate the worst-case propagation delay in the CL stages. The behavior of the combinational logic can then be specified and synthesized without considering timing. Speed Independent (SI) asynchronous circuits are analogous to clocked CL design because SI circuits are independent of time—the behavior will be correct for any arbitrary gate delay.
High-performance circuits, both clocked and asynchronous, benefit from more aggressive timing methodologies. Clocked circuits can treat time locally to allow adaptive and variable time in different parts of the circuit. Timed asynchronous and sequential circuits can have significantly enhanced performance, at the cost of lower robustness to delay variation.
Metric timing requires the specification of either propagation times or of ranges of propagation times. Unfortunately metric timing analysis can explode in complexity even when simple localized timing is used. The synthesis and verification of even moderate-sized timed circuits can therefore become intractable. Further, accurate metric ranges require layout parameters, which may not be present when a circuit is to be synthesized.
What is needed is a system and method of defining a circuit which frees the circuit from a dependence on propagation delays or on estimates of propagation delays while maintaining synthesis and verification of hazard-free designs.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a system and method of performing logic synthesis from a behavioral description of a circuit is described. A signal ordering of signals in the circuit is defined, wherein defining a signal ordering of signals in the circuit includes specifying a relative ordering of a plurality of events within the circuit. The behavioral description is modified as a function of the signal ordering. The circuit is then synthesized as a function of the modified behavioral description.
According to another aspect of the present invention, a system and method of verifying a circuit from a behavioral description of that circuit is described. A signal ordering of signals in the circuit is defined, wherein defining a signal ordering of signals in the circuit includes specifying a relative ordering of a plurality of events within the circuit. The behavioral description is modified as a function of the signal ordering. The circuit is then verified as a function of the modified behavioral description.
According to yet another aspect of the present invention, a circuit includes a plurality of transistors and conductors connecting two or more of the plurality of transistors. The conductors are defined and synthesized as a function of a behavioral description of the circuit, wherein the behavioral description includes information specifying a relative ordering between a plurality of events within the circuit.
According to yet another aspect of the present invention, a computer readable medium includes program code for representing a circuit through a behavioral description of the circuit, program code for defining a signal ordering of signals in the circuit, wherein defining includes specifying a relative ordering of a plurality of events within the circuit, program code for modifying the behavioral description as a function of the signal ordering and program code for synthesizing the circuit as a function of the modified behavioral description.
According to yet another aspect of the present invention, a computer readable medium includes program code for representing a circuit through a behavioral description of the circuit, program code for defining a signal ordering of signals in the circuit, wherein defining includes specifying a relative ordering of a plurality of events within the circuit, program code for modifying the behavioral description as a function of the signal ordering and program code for verifying the circuit as a function of the modified behavioral description.
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Ginosar Ran
Rotem Shai
Stevens Kenneth S.
Intel Corporation
Schwegman Lundberg Woessner & Kluth P.A.
Smith Matthew
Speight Jibreel
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