Circuit structure which avoids latchup effect

Details Circuit structure which avoids latchup effect Circuit structure which avoids latchup effect

1999-05-06

1999-11-23

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257369, 257372, 326 83, 326 15, 326112, 326119, 326121, 327310, 327313, 327576, H01L 2976

Patent

active

059905239

ABSTRACT:
A circuit structure which avoids a latchup effect. An N-well is formed in a P-type substrate. An N-type contact is formed in the N-well. A PMOS is located on the N-well. A gate of the PMOS connects to an input terminal and a source region of the PMOS connects to a voltage source. A first NMOS and a second NMOS are located on the P-type substrate. A gate of the first NMOS connects to the input terminal, a source region of the first NMOS connects to a ground terminal, and a drain region of the first NMOS connects to an output terminal and a drain region of the PMOS. A gate of the second NMOS connects to the output terminal, a source region of the second NMOS connects to a voltage source, and a drain region of the second NMOS connects to the N-type contact.

REFERENCES:
patent: 4209713 (1980-06-01), Satou et al.
patent: 5041894 (1991-08-01), Reczek et al.
patent: 5760631 (1998-06-01), Yu et al.
Hargrove et al., "Latchup in COMS Technology," IEEE 98CH36173, p. 269, Jun. 1998.

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