Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-11
2004-07-13
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S360000, C257S365000, C257S382000, C257S383000
Reexamination Certificate
active
06762466
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a circuit structure for connecting a bonding pad and an electrostatic discharge (ESD) protection circuit. More particularly, the present invention relates a multiple path circuit structure for connecting a bonding pad and an ESD protection circuit such that the multiple paths permit the discharge of a larger current and hence improve circuit protection capacity.
2. Description of Related Art
Electrostatic discharge is a phenomenon that occurs when static charge moves on a non-conducting surface. Sudden movement of electric charges inside the semiconductor material of an integrated circuit (IC) package often leads to circuit failure. For example, somebody walking across a carpet may pick up static charges. If the surrounding air has a high relative humidity (RH), the body of a person may charge up to a few thousand volts. However, if the surrounding air has a low RH, the body of a person may charge up to ten thousand or more volts. IC packaging machines or testing equipment may also accumulate charges and produce from several hundred to several thousand volts of static electricity. As the aforementioned charged bodies (human, machine or equipment) come in contact with a silicon chip, the sudden surge in power due to the sudden movement of static charges through the chip may damage the internal circuits or cause malfunction.
To minimize the damaging effect of electrostatic discharge on integrated circuits, special ESD protection schemes have been developed. The most common method is the provision of a hardware discharge route. In other words, an on-chip ESD protection circuit is provided between the internal circuit and each bonding pad.
FIG. 1
is a schematic cross-sectional view showing a conventional circuit structure that connects an ESD protection circuit with the bonding pad of a semiconductor device.
FIG. 2
is a perspective view of the circuit structure shown in FIG.
1
. Note that the dielectric layers in
FIGS. 1 and 2
are not shown. As shown in
FIGS. 1 and 2
, the bonding pad
100
is formed in the uppermost layer of the semiconductor device and the ESD protection circuit
118
is formed within the substrate
50
. The bonding pad
100
connects sequentially, in a downward direction, with a via
102
, a conductive layer
104
, a second via
106
, a second conductive layer
108
, a third via
110
, a third conductive layer
112
. The third conductive layer
112
has an extension line
112
a
that extends to a region above the drain terminal
116
of the ESD protection circuit
118
. The extension line
112
a
and the drain terminal
116
are connected through a contact
114
. In addition, an insulating layer
130
encloses the aforementioned circuit components and separates the bonding pad
100
from the substrate
50
.
During an electrostatic discharge, static electricity flows from the bonding pad
100
to the ESD protection circuit
118
via an external circuit. In other words, current discharges from the bonding pad
100
via the first via
102
, the first conductive layer
104
, the second via
106
, the second conductive layer
108
, the third via
110
, the third conductive layer
112
, the extension line
112
a
and the drain terminal
116
of the ESD protection circuit
118
. Since static charges are channeled away via the ESD protection circuit
118
, possible damage to the internal circuits is prevented.
According to
FIGS. 1 and 2
, static electricity is discharged through the single metallic layer (that is, the extension line
112
a
) to the ESD protection circuit
118
. When a sufficiently large current flows through the extension line
112
a
, the extension line
112
a
may fuse leading to malfunction of the ESD protection circuit
118
. To prevent the fusing of the extension line
112
a
due to an over-current, width of the extension line
112
a
is increased. However, as semiconductor devices continue to be miniaturized, a widening of line width implies a lowering of processing window as well as level of integration.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a circuit structure for connecting the bonding pad of a semiconductor device with an electrostatic discharge (ESD) protection circuit so that the device has better electrostatic discharge protection.
A second object of this invention is to provide a circuit structure for connecting the bonding pad of a semiconductor device with an electrostatic discharge (ESD) protection circuit such that line width of the conductive connection wire can be reduced, thereby increasing the manufacturing process window.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a circuit structure for connecting a bonding pad with an electrostatic discharge protection circuit. The circuit structure includes a plurality of conductive layers, a plurality of first vias, a first conductive line, a plurality of second conductive lines and a plurality of second vias. The conductive layers are parallel layers each at a different height level between the bonding pad and a substrate. The first vias connect the bonding pad electrically with a neighboring conductive layer as well as each neighboring conductive layer. The first conductive line connects electrically with the conductive layer nearest the substrate and the drain terminal of an ESD protection circuit. The second conductive lines are parallel lines each at a different height level between the first conductive line and the bonding pad. Each second conductive line connects electrically with the conductive layer at a corresponding height level. The second vias connect electrically with the first conductive line and the second conductive line adjacent to the first conductive line as well as each neighboring second conductive line.
In brief, the circuit structure of this invention has a multi-layered path structure consisting of first conductive lines and second conductive lines. Since current may diverge and pass through each of these multiple pathways, current running inside each of these sub-pathways is relatively small. Hence, line width of each conductive line may be reduced so that more flexibility in the circuit design is permitted.
In addition, the presence of multiple paths in the circuit structure has an additional advantage. Even when one of these conductive lines (paths) is accidentally severed, other conductive lines may still conduct current away and hence safeguard against complete failure of ESD protection.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6462384 (2002-10-01), Kwon
Chou Jin-Tau
Huang Shao-Chang
Elms Richard
Menz Douglas
United Microelectronics Corp.
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