Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Patent
1997-05-30
2000-08-29
Dutton, Brian
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
438 11, 438 18, H01L 2358, H01L 2100, H01L 2166, G01R 3126
Patent
active
061112690
ABSTRACT:
A test device for testing an integrated circuit fabricated according to a process is disclosed. The device includes a layout structure, and a excitation circuit. The layout structure includes a plurality of branch structures which are arranged in parallel. Each branch structure includes a feature having a predetermined dimension. The dimension of the feature between associated with adjacent branch structures increases/decreases so as to cover an entire, predetermined spectrum or range of predetermined minimum dimensions. The feature is present (i.e., formed) in a respective branch structure when the process bias/resolution supports fabrication of that dimension. Otherwise, that feature is absent. The excitation circuit is adapted to provide a current through each branch structure to the extent the feature in the branch structure is present. All the branch currents are collected at a common node. If the feature is absent, the current will not be carried, and will thus not contribute to the total current. The accumulated current at the common node is then sunk to a ground node through a resistive shunt to thereby generate a voltage signal defining a process bias signal. The process bias signal is indicative of the process bias, or, in other words, the deviation of the fabrication process in actually resolving a predetermined minimum dimension, from an ideal or nominal dimension.
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Cypress Semiconductor Corp.
Dutton Brian
Maiorana P.C. Christopher P.
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