Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-12-28
2004-04-27
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06728937
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in the Japanese Patent Application No.Hei11-375842 filed in Dec. 28, 1999 in Japan, to which the subject application claims priority under the Paris Convention and which is incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit simulation device for, by using pieces of information related to the element structures and electric characteristics of a plurality of semiconductor elements, predicting the dispersion of circuit characteristics caused by differences of the element structures and the electric characteristics from design values, a circuit simulation method, a circuit simulation program product, and a circuit manufacturing method for, by using pieces of information related to the element structures and electric characteristics of a plurality of semiconductor elements, predicting the dispersion of circuit characteristics caused by differences of the element structures and the electric characteristics from design values, for determining conditions for manufacturing a circuit with reference to the dispersion, and for manufacturing the circuit on the basis of the circuit manufacturing conditions and, more particularly, to a technique for considerably increasing the yield of a circuit manufacturing process.
2. Description of the Related Art
In recent years, with a rapid advance of micropatterning of semiconductor elements, an influence on circuit characteristics caused by differences (=variation in process) of the structures and electric characteristics of semiconductor elements from design values occurring in the process of manufacturing semiconductor elements becomes very conspicuous. For such a background, recently, the following process has been actively performed. That is, the dispersion of circuit characteristics caused by variation in process is predicted by simulation using a computer system, and, with reference to the results, devices and circuits are manufactured.
As a means, which has been proposed up to now, for predicting the dispersion of circuit characteristics caused by variation in process, a means for extracting sets of circuit parameters from the structures and electric characteristics of a plurality of elements which are influenced by the variation in process and for giving the extracted circuit parameter sets to a circuit simulator to obtain a distribution state of the circuit characteristics is generally used.
In the following description, by using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as an example, two concrete examples of conventional dispersion predicting methods for circuit characteristics will be introduced.
In the first dispersion predicting method, a plurality of MOSFETs influenced by variation in process in manufacturing are actually measured, or the dispersion of process conditions is given to a process/device simulator, so that pieces of information related to the element structures and electric characteristics of the MOSFETs. Thereafter, by using the pieces of information related to the element structures and the electric characteristics of the MOSFETs are collected, circuit parameters related to the MOSFETs are extracted in a state that gate lengths L (gate widths W) in analytic model equations of the MOSFETs are fixed to a gate length L
0
(gate width W
0
) which is a design value. Subsequently, a plurality of obtained circuit parameters are given to the circuit simulator, and circuit simulation in a state that the gate lengths (gate widths W) in the analytic model equations of the MOSFETs are fixed to the gate length L
0
(gate width W
0
) which is the design value is performed, so that the dispersion of circuit characteristics of the MOSFETs is evaluated.
In this case, as information given to the circuit simulation, in addition to the circuit parameters, a response surface model (model generated on the basis of Response Surface Methodology) representing circuit parameters by using a pricipal component obtained by performing principal component analysis to circuit parameter sets of the plurality of MOSFETs or a corner model may be given. However, the details of these models are omitted.
The “extraction of circuit parameters” mentioned here means general processes for determining the values of parameters (to be referred to as circuit parameters hereinafter) in such analytic model equations that electric characteristics obtained by collecting the analytic model equations of the MOSFET incorporated in the circuit simulation.
In addition, the “analytic model of the MOSFET” means general equations in which the inter-terminal currents, conductances, capacitances, and terminal charges of the MOSFETs are expressed by the functions of circuit variables such as a terminal bias, gate lengths L, gate widths W, and temperatures T and circuit parameters determined depending on a semiconductor element manufacturing process.
On the other hand, in the second dispersion predicting method, unlike in the first method, when circuit parameters are extracted, gate lengths L (gate widths W) in the analytic model equations of MOSFETs are set to be actual gate lengths Lactual (gate widths Wactual) of the MOSFETs.
Here, when information related to element structures obtained by process/device simulation exists, information related to the actual (=in consideration of variation in process) gate lengths Lactual (gate widths Wactual) can be extracted from the information related to the element structures (more specifically, see PDFAB v2.1 Modeling Reference Manual, PDF Solutions, Inc.). When structure information of real devices exist, the information related to the actual gate lengths Lactual can be extracted by a method in which the sizes of SEM (scanning electron microscope) pictures are measured or other methods.
In this manner, in the conventional circuit manufacturing process, in general, a plurality of circuit parameter sets are extracted from the structures and the electric characteristics of a plurality of elements, and a device manufacturing or circuit manufacturing are performed with reference to a distribution state of circuit characteristics obtained by giving the extracted circuit parameter sets to the circuit simulator. However, the conventional circuit manufacturing process has the following technical problem to be solved.
First, in the conventional circuit manufacturing process, as in the first dispersion predicting method, although the gate lengths and the gate widths of the MOSFETs vary, the gate lengths L (gate widths W) in the analytic model equations are set to be the design values L0 (W
0
) in extraction of circuit parameters. For this reason, the differences (Lerr=Lactual−L
0
, Werr=Wactual−W
0
) between the gate lengths (gate widths W) adversely affect the other circuit parameters. In addition, since the adverse affection changes depending on an extraction strategy of the circuit parameters, parameters which the adverse affection are given cannot be predicted at all. More specifically, in the conventional circuit manufacturing process, since the circuit parameters which are adversely affected by the influence of the errors of the gate lengths and the gate widths cannot be physically and correctly extracted, the circuit characteristics when the gate lengths and the gate widths change cannot be correctly predicted. As a result, the yield of the circuit manufacturing process cannot be improved.
A simple example will be introduced to understand the above problem.
It is assumed that the drain current analytic model equation is given by:
Ids=
(
W/L
)·
U
0
·
A·Vds,
(Equation 1)
and that a drain current Ids is Ids
1
when a drain voltage Vds is Vds
1
.
In this case, when an actual gate length Lactual is given, (equation 1) is given by:
Ids
1
=(
W/Lactual
)·
U
01
·
A·Vds
1
.
(equation 2)
For this reason, by using the value of a parameter value U
0
, a value U
01
which reflects v
Wakita Naoki
Yamaguchi Tetsuya
Bowers Brandon
Holmes Brenda O.
Kilpatrick & Stockton LLP
Siek Vuthe
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