Circuit redundancy having a variable impedance circuit

Details Circuit redundancy having a variable impedance circuit Circuit redundancy having a variable impedance circuit

1993-09-30

1995-03-07

Hudspeth, David R.

Electronic digital logic circuitry

Reliability

Redundant

365200, 326 21, H03K 19003

Patent

active

053961242

ABSTRACT:
In a semiconductor memory having a redundant circuit, a plurality of first normal cells and a plurality of first spare cells are connected to a first pair of data lines, and a plurality of second normal cells and a plurality of second spare cells are connected to a second pair of data lines. Both pairs of data lines are connected to an output data line through a selecting amplifier. A normal cell is selected based on a combination of NGWL1, NGWL2, . . . with BLK1, BLK2, both NGWL1, NGWL2, . . . and BLK1, BLK2 being supplied from a decoder, and a spare cell is selected based on a combination of the BLK1, BLK2 supplied from the decoder with SGWL1, SGWL2, . . . supplied from a redundancy judging circuit. A second spare cell is selected when a first normal cell is selected, and a first spare cell is selected when a second normal cell is selected. Only at the time when a spare address is entered, one of the SGWL1, SGWL 2, . . . is raised. This not only achieves a high-speed reading and a high defect-relief rate, but also reduces the current consumption and the chip area.

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K. Sasaki et al., "A 9 ns 1 Mb CMOS SRAM", ISSCC Digest of Technical Papers, pp. 34-35 (1989).

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