Circuit reduction technique for improving clock net analysis...

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis

Reexamination Certificate

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Details

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S014000

Reexamination Certificate

active

06895524

ABSTRACT:
A method for reducing a transistor circuit netlist for clock network timing verification is provided. Further, a simulation tool that reduces a transistor circuit netlist such that nonlinear circuit properties are preserved is provided. Further, a computer system that improves clock network performance by simulating a netlist that is generated from a reduced transistor circuit netlist is provided.

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