Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-05-18
2004-06-22
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C438S612000
Reexamination Certificate
active
06753609
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication technology, and more particularly, to a method of forming circuit probing (CP) contact points on fine pitch peripheral bond pads (PBP) on a flip chip for the purpose of facilitating peripheral circuit probing of the internal circuitry of the flip chip.
2. Description of Related Art
The flip-chip technology is an advanced semiconductor fabrication technology that allows the overall package size to be made very compact. The flip-chip package configuration differs from conventional ones particularly in that it mounts the semiconductor chip in an upside-down manner over the chip carrier and electrically coupled to the same by means of solder bumps provided on the active surface of the semiconductor chip. Since no bonding wires are required, which would otherwise occupy much layout space, the overall size of the flip-chip package can be made very compact as compared to conventional types of semiconductor device packages.
The attachment of solder bumps to a flip chip requires the provision of the so-called UBM (Under Bump Metallization) pads on the active surface of the semiconductor chip, which is wettable to the solder bumps so that the solder bumps can be securely attached to the flip chip.
A great variety of patented technologies have been proposed for the fabrication of UBM pads on a flip chip. A few of these patented technologies are listed in the following:
U.S. Pat. No. 5,904,859 entitled “FLIP CHIP METALLIZATION”;
U.S. Pat. No. 5,902,686 entitled “METHODS FOR FORMING AN INTERMETALLIC REGION BETWEEN A SOLDER BUMP AND AN UNDER BUMP METALLURGY LAYER AND RELATED STRUCTURES”,
U.S. Pat. No. 6,015,652 entitled “MANUFACTURE OF FLIP-CHIP DEVICE”;
U.S. Pat. No. 5,137,845 entitled “METHOD OF FORMING METAL CONTACT PADS AND TERMINALS ON SEMICONDUCTOR CHIPS”
U.S. Pat. No. 5,773,359 entitled “INTERCONNECTION SYSTEM AND METHOD OF FABRICATION”;
U.S. Pat. No. 5,736,456 entitled “METHOD OF FORMING CONDUCTIVE BUMPS ON DIE FOR FLIP CHIP APPLICATIONS”;
U.S. Pat. No. 4,927,505 entitled “METALLIZATION SCHEME PROVIDING ADHESION AND BARRIER PROPERTIES”;
U.S. Pat. No. 5,903,058 entitled “CONDUCTIVE BUMPS ON DIE FOR FLIP CHIP APPLICATION”.
Siliconware Precision Industries Co., Ltd., (SPIL), which is Applicant of this invention, presently utilizes a triple-layer UBM structure for flip chip application, which includes a bottom layer of aluminum (Al), an intermediate layer of nickel-vanadium (NiV), and an upper layer of copper (Cu). The use of this Al/NiV/Cu metallization structure, however, would result in a fabrication problem when it is also used for the forming of an array of circuit probing contact points on peripheral bond pads on the flip chip that are spaced at a fine pitch of less than 70 &mgr;m (micrometer), typically 60 &mgr;m or 50 &mgr;m. This fabrication problem is illustratively depicted in the following with reference to
FIG. 1
,
FIG. 2
,
FIGS. 3A-3G
, and FIG.
4
.
FIG. 1
is a schematic diagram showing the active surface of a flip chip semiconductor substrate
10
where a plurality of peripheral bond pads (PBP)
11
are formed. In the case of the PBPs
11
being spaced at a fine pitch of less than 70 &mgr;m, they would be unsuited for solder-bump attachment due to the fact that solder bumps are relatively large in size and such a fine pitch would make neighboring solder bumps to come in touch with each other. Therefore, as a solution to this problem, the PBPs
11
are redistributed via re-distribution layers (RDL)
12
to new locations called area array pads (AAP)
13
.
Referring further to
FIG. 2
, each PBP
11
, RDL
12
, and AAP
13
is covered by a passivation layer
20
; and a UBM pad
30
is formed over the AAP
13
for attachment to a solder bump
50
. This allows the internal circuitry of the semiconductor substrate
10
to be electrically connected to an external printed circuit board (not shown) via the conductive path consisting of the PBP
11
, the RDL
12
, the AAP
13
, the UBM pad
30
, and the solder bump
50
.
During the flip chip fabrication, it is required to perform a circuit probing (CP) procedure to the semiconductor substrate
10
for the purpose of checking whether the internal circuitry thereof would operate normally. The CP procedure can be performed by using a PBP-dedicated probing card (not shown) which is designed to be electrically coupled to the internal circuitry of the semiconductor substrate
10
via the PBP
11
. However, after the PBP
11
is redistributed to the AAP
13
and covered by the passivation layer
20
, the PBP-dedicated probing card (not shown) would become useless; and instead, it requires the use of an AAP-dedicated probing card that is specifically designed to be electrically coupled to the internal circuitry of the semiconductor substrate
10
via the AAP
13
.
One drawback to the use of the AAP-dedicated probing card, however, is that it is much more expensive to purchase than the PBP-dedicated probing card. Therefore, it would be highly cost-ineffective to perform a CP procedure by using AAP-dedicated probing card.
One solution to the foregoing problem is to break open the part of the passivation layer
20
that is laid directly over the PBP
11
and form an exposed metallization layer (not shown in
FIG. 2
) over the PBP
11
to serve as a peripheral CP contact point, so that the PBP-dedicated probing card can be nevertheless employable for use to perform a CP procedure to the internal circuitry of the semiconductor substrate
10
without having to purchase expensive AAP-dedicated probing card. A realization of this solution through the Al/NiV/Cu metallization technology is depicted in the following with reference to
FIGS. 3A-3G
.
Referring to
FIG. 3A
, in the flip chip fabrication, the first step is to prepare a semiconductor substrate
10
, such as a silicon substrate. Next, a PBP
11
, an RDL
12
, and an AAP
13
are formed from aluminum (Al) at predefined locations on the active surface of the semiconductor substrate
10
. The PBP
11
, the RDL
12
, and the AAP
13
are fabricated through conventional processes which are not within the spirit and scope of the invention, so detailed steps thereof will not be described.
Referring further to
FIG. 3B
, in the next step, a passivation layer
20
is formed from an electrically-insulative material over the semiconductor substrate
10
to a predefined thickness that allows the passivation layer
20
to cover the entirety of the PBP
11
, the RDL
12
, and the AAP
13
. Further, the passivation layer
20
is selectively removed to form a first opening
21
to expose the PBP
11
and a second opening
22
to expose the AAP
13
.
Referring further to
FIG. 3C
, in the next step, an Al/NiV/Cu metallization structure
30
is formed over the passivation layer
20
to a predefined thickness, which includes an upper layer of copper (Cu)
30
a,
an intermediate layer of nickel-vanadium (NiV)
30
b,
and a bottom layer of aluminum (Al)
30
c.
The Al/NiV/Cu metallization structure
30
is formed by first depositing aluminum over the passivation layer
20
to form the aluminum layer
30
c,
then depositing nickel-vanadium over the aluminum layer
30
c
to form the nickel-vanadium layer
30
b,
and finally depositing copper over the nickel-vanadium layer
30
b
to form the copper layer
30
a.
Referring further to
FIG. 3D
, in the next step, a photoresist layer
40
is coated over the Al/NiV/Cu metallization structure
30
to a predefined thickness that allows the photoresist layer
40
to cover the entire top surface of the Al/NiV/Cu metallization structure
30
. This photoresist layer
40
is then to be selectively removed through a photolithographic and etching process to mask only those portions of the Al/NiV/Cu metallization structure
30
that are laid directly above the PBP
11
and the AAP
13
.
In practice, the photolithographic and etching process can be implemented through the use of various kinds of equipment, such as high-resolution stepper and dry-etching machine, or lo
Chien Feng-Lung
Ke Chun-chi
Lo Randy H. Y.
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Nelms David
Siliconware Precision Industries Co. Ltd.
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