Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
1999-08-30
2002-11-12
Whitehead, Jr., Carl (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S667000, C257S786000
Reexamination Certificate
active
06479887
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit pattern tape for semiconductor packages, and a semiconductor package produced using the novel circuit pattern tape. More particularly, the present invention relates to a circuit pattern tape that is particularly adapted for use in the wafer-scale production of chip size semiconductor packages.
2. Description of the Related Art
As a result of the recent trend in the consumer and industrial electronics markets toward designs that are higher in performance, yet more compact in size, such as communication devices and computers, a demand has arisen for semiconductor packages that have substantially higher input/output pin densities, yet which are simpler and more compact, for use in such devices.
This demand has resulted in the development of a semiconductor package having a size that is nearly the same as that of the semiconductor chip packaged therein. This style of package is referred to in the industry as a “chip size,” or a “chip scale,” or a “chip-on-board” semiconductor package. Currently, the demand for such semiconductor packages is increasing.
Chip size semiconductor packages are fabricated at a wafer scale level by laminating a circuit pattern tape having a plurality of individual circuit pattern units in it onto the surface of a semiconductor wafer having a plurality of corresponding individual semiconductor dies, or “chip” units, in it, to form an assembly, followed by the application to the laminated assembly of a well-known packaging process involving, typically, a wire bonding process for electrically connecting the circuit patterns of the circuit pattern tape to die pads on the semiconductor chips in the wafer, a resin molding process for encapsulating the wire bonding areas of the wafer within a protective resin envelope, a solder ball attachment process for attaching solder balls that are used as external input/output terminals of the package to the wafer, and lastly, a “singulation” process, wherein the processed wafer assembly is cut apart to divide the assembly into a plurality of finished, individual semiconductor packages.
FIG. 16A
is a plan view of a conventional circuit pattern tape
10
′ for semiconductor packages. A plurality of individual circuit pattern units
11
are formed in the circuit pattern tape, the units corresponding on a one-to-one basis to a plurality of individual chip units
3
formed in a semiconductor wafer
2
(see FIG.
17
A). Each circuit pattern unit
11
has its own independent, conductive circuit pattern. An insulative solder mask
19
is formed over selected portions of the conductive circuit patterns on the tape, as described below.
FIG. 16B
is a magnified view of the circled portion F of the tape shown in FIG.
16
A. In the illustrated portion, four identical circuit pattern units
11
are shown joined together at their edges. In
FIG. 16B
, the reference numeral
12
denotes conductive traces. The solder mask
19
includes openings in it through which one end of each of the conductive traces
12
is exposed. The exposed end of each conductive trace
12
is connected to a solder ball land
13
to which a solder ball (not shown) is attached. Each conductive trace
12
is connected at its other end to an associated one of a plurality of bond fingers formed within a bond finger region
15
. A plurality of such conductive traces
12
form the circuit pattern of each circuit pattern unit
11
.
The bond finger regions
15
, like the solder ball lands
13
, are not covered by the solder mask
19
, so that the bond fingers
14
are left exposed. An opening region
16
′ is defined within each bond finger formation region
15
. The opening regions
16
′ are punched to form openings
16
prior to laminating the circuit pattern tape
10
′ onto the wafer
2
. Die bonding pads
4
(see
FIG. 17B
) on each semiconductor chip unit
3
are upwardly exposed through an associated one of openings. The exposed die pads are connected to respective bond fingers
14
by means of fine, conductive bonding wires
40
(see FIG.
19
).
In
FIG. 16B
, reference numeral
17
denotes high-current-density “bus” lines. The bus lines
17
are used in an electrolytic or electroless plating process to form a nickel (Ni)/gold (Au) plating on the solder ball lands
13
and/or on the bond fingers
14
. The Ni/Au plating makes it easy to attach the solder balls (not shown) to the lands
13
, and/or to bond the bonding wires (see
FIG. 19
) to the bond fingers
14
, respectively. The bus lines
17
are later removed when the wafer is singulated, or cut, along the singulation lines
21
, which disconnects the conductive traces
12
from each other electrically.
When chip size semiconductor packages are fabricated using the conventional circuit pattern tape
10
′ described above, it is difficult to accurately determine the cutting line for singulation of the circuit pattern units
11
because the space between adjacent circuit pattern units
11
is extremely narrow. As a result, even when there is only a microscopic error in the determination of the cutting line, the bus lines
17
may be only partially removed. This can result in a problem, in that a number of defective semiconductor packages may be produced as a result.
FIG. 16C
is a cross-sectional view taken along the line VII—VII in FIG.
16
A.
FIG. 16D
is a cross-sectional view taken along the line VIII—VIII in FIG.
16
B.
FIGS. 16C and 16D
respectively illustrate the cross-sectional structure of the conventional circuit pattern tape
10
′. The lowermost layer of the tape structure is an insulating polyimide layer
18
. Conductive traces
12
and solder ball lands
13
are formed on the surface of the polyimide layer
18
. Bond fingers
14
are also formed on the polyimide layer
18
around the respective openings
16
. The solder mask
19
is formed over the conductive traces
12
. The solder ball lands
13
and bond fingers
14
are upwardly exposed through openings in the solder mask
19
. At the peripheral region of each circuit pattern unit
11
, a thin, conductive metal film
12
′ is laminated over the polyimide layer
18
. The solder mask
19
also covers the thin, conductive metal film
12
′.
In the conventional circuit pattern tape
10
′ described above, only the bond fingers
14
, which receive output signals from an associated semiconductor chip
3
(see FIG.
19
), are formed in the bond finger regions
15
of each circuit pattern unit
11
, as shown in
FIGS. 16B and 16D
. For this reason, in order to provide ground bonding of ground signals from respective semiconductor chips, it is necessary to connect together a number of the conductive traces
12
connected to the bond fingers
14
, for example, by electrically connecting together a number of the solder ball lands
13
. As a result of this, the circuit pattern has a reduced spatial redundancy for the formation of the circuit pattern, i.e., the conductive traces
12
, at each of the regions where such a grounding connection is made. Furthermore, the bond fingers that are to be ground-bonded must be disposed at locations that correspond to the ground signal locations. This can severely limit the freedom of design of the circuit tape pattern, and results in a limitation on the number of die bonding pads on the associated semiconductor chips that can be effectively accommodated.
FIG. 17A
is a plan view of a typical wafer
2
partitioned into a plurality of semiconductor chip units
3
by singulation lines
21
. The singulation lines
21
may be real or imaginary, and typically consist of lines, or “streets,” scribed in the surface of the wafer
2
.
FIG. 17B
is a magnified view of the circled portion G in FIG.
17
A.
FIGS. 17A and 17B
illustrate wire bonding die pads
4
formed on the active surface of each semiconductor chip unit
3
. It should be understood that the arrangement of the die pads
4
shown is intended for illustrative purposes only, as the die pads
4
may be arranged in one o
Kang Dae-Byung
Yoon Ju-Hoon
Amkor Technology Inc.
Jr. Carl Whitehead
Rose Kiesha
LandOfFree
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