Circuit pattern design method, circuit pattern design...

Details Circuit pattern design method, circuit pattern design... Circuit pattern design method, circuit pattern design...

2001-06-12

2003-05-06

Nelms, David (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06560768

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-177309, filed Jun. 13, 2000; and No. 2001-090457, filed Mar. 27, 2001, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a circuit pattern design method, circuit pattern design system, and recording medium used for character projection type charged-particle beam exposure.
Electron beam exposure is an effective means for processing the micropattern of a semiconductor circuit. A Variable Shaped Beam (VSB) exposure method as a typical electron beam exposure method divides a circuit pattern into small rectangles or triangles and repetitively exposes them, which increases the number of electron beam shots and decreases the throughput.
To prevent this, a CP (Character Projection) exposure method of shaping an electron beam into the shape of a figure with a size of several micro meter square that can be irradiated with one shot and exposing a figure (character) at once is adopted to decrease the number of shots and increase the throughput.
FIG. 12
shows the schematic arrangement of an electron beam exposure apparatus. As shown in
FIG. 12
, an electron beam
902
emitted by an electron gun
901
is shaped into a square by a first shaping aperture
903
. The shaped electron beam
902
irradiates via a character selection deflector
904
a character which is a transmission window formed in a CP aperture mask
905
. The electron beam
902
having passed through the transmission window with the shape of the character is reduced by a reduction lens
906
and irradiates a desired position on a sample
908
via an objective deflector
907
.
The electron beam is shaped by the CP aperture mask having character-shaped apertures. In a general electron beam exposure apparatus, the number of characters which can be arranged within the deflection region of the character selection deflector is about 100 at most.
A method of designing the circuit pattern of a semiconductor product such as an ASIC or system LSI, and a flow up to electron beam exposure will be described with reference to the flow chart of FIG.
13
.
FIG. 13
is a flow chart showing a conventional circuit pattern design method and exposure method.
FIG. 13
shows only steps closely related to this proposition while timing analysis, circuit optimization, and various verifications are omitted.
(Step S
401
)
The electronic circuit of a semiconductor device is described. This is generally described by using HDL (Hardware Description Language). Among HDL descriptions, an RTL (Register Transfer Level) description which describes the arrangement and operation of a logic circuit between registers is often used.
(Step S
402
)
Logic synthesis is done based on the described RTL, device characteristics such as an operation frequency, and design constraint conditions such as a chip area. A logic circuit which satisfies the design constraints is generated, and circuit patterns are synthesized based on this logic circuit. The logic circuit is synthesized by assigning functions to standard cells which optimize circuit patterns for functional units such as a logic gate and flip-flop. The patterns of the standard cells are laid out on a chip, and the standard cells are wired each other (Place and Route: P&R).
(Step S
403
)
Steps S
401
and S
402
and various verifications are performed, and device pattern data is released in the GDSII STREAM format.
(Step S
404
)
The process engineer who actually manufactures a device receives the pattern data from the designer.
(Step S
405
)
Figures which are repetitively used and can serve as characters in CP exposure are extracted from the figures contained in the pattern data. The figures are assigned to characters subjected to CP exposure method by the number of characters which can be set on an exposure apparatus. The remaining figures are exposed by VSB exposure method.
(Step S
406
)
A CP aperture mask is prepared based on the character information extracted in step S
405
.
(Step S
407
)
The pattern data is converted into exposure data which can be input to an electron beam exposure apparatus in use on the basis of the pieces of information in steps S
405
and S
406
.
(Step S
408
)
The CP aperture mask formed in step S
406
is set in the apparatus, the exposure data generated in step S
407
is input to the apparatus (or the controller of the exposure apparatus), and electron beam exposure is executed.
(Step S
409
)
A sample such as a resist film on a Si wafer or mask blanks exposed with an electron beam is extracted from the exposure apparatus, heated, and developed to form a resist pattern.
In this method, a circuit pattern designed by the designer does not consider characters in CP exposure method with electron beam. The process engineer extracts figures serving as CP exposure units from pattern data released by the designer and assigns the figures to characters.
A standard cell library which contains standard cells used in step S
402
of
FIG. 13
generally includes several hundred types of standard cells. In character extraction of step S
405
, standard cells serving as the constituting units of logic circuits which constitute a circuit pattern are assigned as characters to be exposed by CP exposure method. As a result, the number of characters necessary for exposing all figures by CP exposure method increases. To prevent this, only some of the figures of the pattern are exposed by CP exposure method, and the remaining figures are exposed by the VSB exposure method of dividing a figure into small rectangles. In a logic device such as an ASIC, the ratio of VSB exposure method is higher than in a device such as a memory including repetitively used figures at high ratio, so even the CP exposure method cannot effectively decrease the number of shots and increase the throughput.
Extensive studies have been made to increase the number of characters laid out on an aperture mask. However, high-precision development is difficult to achieve, and equipment must be installed instead of existing apparatuses, resulting in high cost.
BRIEF SUMMARY OF THE INVENTION
(1) There is provided a circuit pattern design method which uses a plurality of standard cells that optimize circuit patterns for function units on the basis of a logic description which describes circuit operation of a semiconductor device, and which method generates a circuit pattern corresponding to charged-particle beam exposure using both a character projection exposure method and a variable shaped beam method, wherein the circuit pattern satisfies a design constraint condition, and a predetermined condition imposed on transfer to a sample or imposed on an aperture mask used in exposure by the character projection exposure method.
(2) According to the present invention, there is provided a charged-particle beam exposure method comprising preparing a circuit pattern design and a character projection (CP) aperture data, the circuit pattern design being prepared using a plurality of standard cells having circuit patterns optimized for function units on the basis of a logic description of circuit operation of a semiconductor device, and corresponding to charged-particle beam exposure using both a character projection exposure method and a variable shaped beam exposure method; and preparing a new CP aperture mask or selecting an appropriate CP aperture mask from existing CP aperture masks on the basis of the CP aperture data; wherein the preparing the circuit pattern design and the CP aperture data includes: generating one or more provisional circuit patterns while gradually decreasing a number of standard cells to be used, determining whether the generated one or more provisional circuit patterns satisfy a design constraint condition, extracting a standard cell used in at least one of said one or more provisional circuit patterns which is determined as satisfying the design constraint condition, in consideration of a la

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