Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2008-07-29
2008-07-29
Malsawma, Lex (Department: 2892)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C205S080000
Reexamination Certificate
active
11334172
ABSTRACT:
A circuit package includes a substrate having an opening and a single unitary heat sink adapted to effectively dissipate heat is positioned in the opening to expose top and bottom surfaces which are respectively coplanar with top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.
REFERENCES:
patent: 3577038 (1971-05-01), Cook, Jr.
patent: 3956052 (1976-05-01), Koste et al.
patent: 3956726 (1976-05-01), McCarthy et al.
patent: 4464420 (1984-08-01), Taguchi et al.
patent: 4693649 (1987-09-01), Harwood et al.
patent: 4703339 (1987-10-01), Matsuo
patent: 5014904 (1991-05-01), Morton
patent: 5031029 (1991-07-01), Acocella et al.
patent: 5057906 (1991-10-01), Ishigami
patent: 5227662 (1993-07-01), Ohno et al.
patent: 5235211 (1993-08-01), Hamburgen
patent: 5285352 (1994-02-01), Pastore et al.
patent: 5430331 (1995-07-01), Hamzehdoost et al.
patent: 5440169 (1995-08-01), Tomita et al.
patent: 5530295 (1996-06-01), Mehr
patent: 5532070 (1996-07-01), Takahashi et al.
patent: 5703399 (1997-12-01), Majumdar et al.
patent: 5751063 (1998-05-01), Baba
patent: 5790379 (1998-08-01), Kang
patent: 5900673 (1999-05-01), Nishi et al.
patent: 5920458 (1999-07-01), Azar
patent: 6191478 (2001-02-01), Chen
patent: 6239487 (2001-05-01), Park et al.
patent: 6281574 (2001-08-01), Drake et al.
patent: 6361857 (2002-03-01), Saito et al.
patent: 6432750 (2002-08-01), Jeon et al.
patent: 6471822 (2002-10-01), Yin et al.
patent: 6563696 (2003-05-01), Harris et al.
patent: 6780672 (2004-08-01), Steele et al.
patent: 2002/0140085 (2002-10-01), Lee et al.
patent: 2004/0021217 (2004-02-01), Epitaux et al.
patent: 5-294744 (1993-11-01), None
patent: 6-37250 (1993-12-01), None
patent: 6-291362 (1994-10-01), None
patent: 8-204120 (1996-08-01), None
patent: 9-102580 (1997-04-01), None
patent: 9-139461 (1997-05-01), None
patent: 2000-138342 (2000-05-01), None
“Thermal VIA/BGA”, Micro Substrates Corporation, website, 3 pages, ©2000, found at: http://www.microsubstrates.com/body—thermal%20via—bga.html.
Technical Schematic entitled “Modification of Ceramic Detail, Thickness & Base,” dated Jan. 29, 2003, Kyocera Corporation.
Bennett Jeffrey A.
Finot Marc
Kohler Robert
Lake Rickie C.
Nguyen Tam
Intel Corporation
Malsawma Lex
Marshall & Gerstein & Borun LLP
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