Circuit optimization system

Details Circuit optimization system Circuit optimization system

1999-03-22

2001-06-26

Phan, Trong (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06253351

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a circuit optimization system for synthesizing a circuit like CMOS or LSI on the level of individual transistors in designing the circuit.
Thanks to recent marvelous development in semiconductor device manufacturing technologies, a so-called “system-on-chip” is now prevailing in the art. That is to say, various functions of an overall system, like computer or telecommunication unit, can be incorporated into a single-chip semiconductor integrated circuit. Also, semiconductor device manufacturing technologies have lately been alternating their generations one after another at even shorter intervals than what they used to be. As a result, it has become a lot easier and much preferred to implement a system-on-chip using such downsized components. Moreover, a semiconductor chip now has to meet a multiplicity of requirements, like low power dissipation, high performance and cost reduction, either selectively or simultaneously, depending on the applications and the operating conditions of specific systems. Accordingly, in order to cope with such a wide variety of demands, multiple sets of techniques should be prepared beforehand in manufacturing a semiconductor integrated circuit.
If the number of variant semiconductor device manufacturing processes or the size of an overall system is increased, then the number of processing steps should also be increased in designing a semiconductor system. Thus, designing techniques should be innovated to reduce such an increased number of designing process steps. According to a most promising measure to reduce the number of designing process steps, circuits having an equivalent function are utilized as recyclable components irrespective of a specific semiconductor device manufacturing process.
Such recyclable functional circuits or layout components are called “hard IP's”. In order to recycle these hard IP's, a variety of techniques, including layout compaction and layout synthesis, may be employed. In accordance with a layout compaction technique, the layout can be automatically modified if the design rule employed in a semiconductor device manufacturing process is changed, as disclosed in Japanese Laid-Open Publication No. 10-3491, for example. On the other hand, in accordance with a layout synthesis technique, various types of layouts are represented by respective parameters associated with individual design rules. Furthermore, if a semiconductor device manufacturing process is modified, then an optimum size of a transistor changes correspondingly. Thus, a method of combining a transistor sizing technique (see, for example, Japanese Laid-Open Publication No. 11-3973) with a layout compaction technique has also been proposed.
However, in accordance with conventional techniques for recycling hard IP's, the structure of a circuit cannot be changed. Accordingly, if a circuit structure to be recycled does not fit in with new conditions imposed by updated process technologies, then the circuit is no longer optimal.
SUMMARY OF THE INVENTION
An object of the present invention is providing a system that can cope with any modification in manufacturing conditions or operating environment by automatically converting a circuit in question into an alternate circuit optimized to comply with that modified conditions or environment.
In order to achieve this object, according to the present invention, if process technology has been modified, then equivalency conversion is carried out while changing part of a circuit once synthesized (hereinafter, simply referred to as a “partial circuit”) to optimize the data of the circuit.
A first circuit optimization system according to the present invention is adapted to optimize a transistor-level circuit, consisting of a plurality of partial circuits each including a plurality of transistors, to comply with process technology associated with the circuit. The system includes equivalent circuit converting means for provisionally converting at least one of the partial circuits, which complies with an equivalency conversion rule of the circuit, into an equivalent circuit having a function equivalent to that of the partial circuit. The system also includes estimate calculating means for calculating an estimate representing a degree of compatibility of the equivalent circuit with the process technology. And the system further includes circuit optimizing means for evaluating the estimate, derived by the calculating means, and for deciding that the partial circuit should be converted into the equivalent circuit if the estimate has improved.
In the first circuit optimization system, if the estimate derived has improved from what it used to be before the conversion, the equivalent circuit can be adopted for circuit synthesis. Accordingly, even if process technology has been modified, circuit data, meeting the requirements of the new process technology, can be re-synthesized.
In one embodiment of the present invention, the converting means preferably includes: an identifier for identifying at least one partial circuit, which is convertible into an associated equivalent circuit thereof, from the partial circuits; and a converter for converting the partial circuit, which has been identified as convertible by the identifier, into the associated equivalent circuit thereof.
In such an embodiment, even if the data about the transistor-level circuit has an enormous quantity, a target partial circuit, complying with the equivalency conversion rule of the circuit, can be identified and converted with much more certainty.
A second circuit optimization system according to the present invention is also adapted to optimize a transistor
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level circuit consisting of a plurality of partial circuits each including a plurality of transistors. The system includes circuit optimization means for optimizing the circuit by converting each of these partial circuits into an associated equivalent circuit thereof having a function equivalent to that of the partial circuit in accordance with an equivalency conversion rule of the circuit.
In the second circuit optimization system, if an equivalency conversion rule, complying with the process technology, has been selected, circuit data can be optimized quickly and easily to comply with the process technology.
A third circuit optimization system according to the present invention is also adapted to optimize a transistor-level circuit to comply with process technology associated with the circuit. The system includes circuit editing means, provided with an input/output section, for interactively modifying the circuit in accordance with an equivalency conversion rule of the circuit. The system also includes estimate calculating means for calculating an estimate to optimize the circuit modified by the circuit editing means in accordance with the process technology. And the system further includes display means for displaying the estimate derived by the calculating means thereon.
In the third circuit optimization system, an operator of the system can interactively modify the circuit using the circuit editing means and can calculate an estimate for optimizing the equivalent circuit obtained by modifying the circuit using the circuit editing means based on the equivalency conversion rule thereof. And then, the operator can output the estimate to the output of the circuit editing means. Accordingly, since the operator can check the estimate of the equivalent circuit just after the modification, artificial errors of the operator can be prevented with a lot more certainty. As a result, the work efficiency can be improved in manually optimizing circuit synthesis.
In an exemplary embodiment of the first or third circuit optimization system, the calculating means preferably includes: a threshold-to-power ratio calculator; a delay calculator; a logical threshold voltage calculator; and an estimate calculator. The threshold-to-power ratio calculator calculates a ratio of the sum of respective threshold voltages of a plurality of serially connected tra

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