Circuit optimization for minimum path timing violations

Details Circuit optimization for minimum path timing violations Circuit optimization for minimum path timing violations

2001-11-30

2004-03-02

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06701505

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to integrated circuit design and more specifically to methods and systems for optimizing delay insertions for reducing timing violations in integrated circuit design.
BACKGROUND OF THE INVENTION
Designers use software tools to perform timing analysis on integrated circuit designs. The software tools can determine if a signal arrives too early or too late at the end of a timing path. The end of the timing path usually consists of either an I/O pin or an input pin of a sequential logic (e.g., a register or latch). When the end of the timing path consists of an input pin of a sequential logic, the early signal causes a setup time violation while the late signal causes a hold time violation. A setup time violation occurs when the signal fails to be present and unchanged at the input pin of the sequential logic for a specified time before the sequential logic is clocked. A hold time violation occurs when the signal fails to remain unchanged at the input terminal of the sequential logic for a specified time after the sequential logic element is clocked. Both setup and hold times must be satisfied for the sequential logic to propagate the appropriate output signal. When the end of the timing path is an I/O pin, the early and late signals fail to meet I/O timing constraints (e.g., board-level constraints between integrated circuit chips).
FIG. 6
shows that the signal to the end of the timing path must arrive within a timing window in each clock cycle (i.e., the signal to the input pin of the sequential logic or the I/O pin must transition within a window in each clock cycle) to avoid timing violations. This timing window is defined by a minimum required time (mRT) after the start of a clock cycle and a maximum required time (MRT) before the end of the same clock cycle. The minimum and the maximum required times are respectively determined from the hold and setup times of a sequential logic or I/O timing constraints imposed by external logic.
When the signal arrives too late at the end of the timing path, the timing violation is referred to as a “max path violation” because the maximum required time of the timing path has been violated. To fix the max path violation, the signal needs to be sped up to avoid a timing violation. Typically a conventional method fixes the max path violation by moving or resizing the logic elements in a timing path, deleting buffers, restructuring the logic, or re-synthesizing the integrated circuit design.
When the signal arrives too early at the end of the timing path, the timing violation is referred to as a “min path violation” because the minimum required time of the timing path has been violated. To fix the min path violation, the signal needs to be delayed to avoid a timing violation. Typically a conventional method fixes the min path violation by placing a buffer in between two elements in the timing path hereafter called “driver” and “receiver”.
The conventional method places the buffer within a bounding box that encloses the driver and receiver. The conventional method attempts to select a buffer with an intrinsic delay (i.e., a delay generated by the buffer without an effective capacitive load at its output pin) equal to a required minimum delay D (
FIG. 6
) for the signal to arrive after the start of the timing window. When the intrinsic delays of the available buffers do not match the required minimum delay D, the conventional method selects the next largest buffer with an intrinsic delay greater than the required minimum delay D. The use of a larger buffer increases the cost of the integrated circuit because the larger buffer increases the size of the integrated circuit. Thus, what are needed are methods and systems that optimize delay insertions between drivers and receivers using available buffers to generate the required minimum delay D.
SUMMARY
A method is provided to optimize delay insertions for reducing a timing violation in a timing path. The method includes inserting a buffer in the timing path between a driver and a receiver and placing the buffer either inside or outside a bounding box that encloses the driver and the receiver. The placement of the buffer inside or outside the bounding box creates the appropriate effective loading on the buffer to generates a minimum delay required to avoid the timing violation.


REFERENCES:
patent: 5764528 (1998-06-01), Nakamura
patent: 6434731 (2002-08-01), Brennan et al.
patent: 6487697 (2002-11-01), Lu et al.
patent: 6513149 (2003-01-01), Donato
patent: 6591407 (2003-07-01), Kaufman et al.
patent: 2003/0101399 (2003-05-01), Yoshikawa

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