Circuit operation verification device and method

Details Circuit operation verification device and method Circuit operation verification device and method

2007-06-05

2007-06-05

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10935271

ABSTRACT:
A circuit verification device includes emulators to which circuit portions obtained by dividing the circuit are implemented. The emulators communicate with each other through a bus to verify the functional operation of the circuit. The circuit is divided based on a communication occurrence pattern between circuit units so that the number of communications occurring between circuit portions is minimized. The input signals of the bus are preferably arranged in the bus address space in descending order of a signal change rate, and a burst transfer may be utilized. Through paths within the circuit being verified are searched, and a plurality of circuit units is divided so as to minimize the number of through paths among the circuit portions.

REFERENCES:
patent: 6106567 (2000-08-01), Grobman et al.
patent: 6279146 (2001-08-01), Evans et al.
patent: 6591402 (2003-07-01), Chandra et al.
patent: 2003/0126563 (2003-07-01), Nakajima
patent: 2000-215226 (2000-08-01), None

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