Circuit on a printed circuit board

Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices

Reexamination Certificate

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C361S792000, C361S795000

Reexamination Certificate

active

07742315

ABSTRACT:
The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring.In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to providea) an additional capacitance for a given signal wiring in a discontinuity section,b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.

REFERENCES:
patent: 6084779 (2000-07-01), Fang
patent: 6198362 (2001-03-01), Harada et al.
patent: 6900992 (2005-05-01), Kelly et al.
patent: 7068518 (2006-06-01), Ueno et al.
patent: 7091571 (2006-08-01), Park et al.
patent: 7235457 (2007-06-01), Forbes et al.
patent: 7355125 (2008-04-01), Becker et al.
T.J. Slegel et al. “The IBM eServer z990 Microprocessor”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 295-309.
G. Gerwig et al. “The IBM eServer z990 Floating-Point Unit”, IBM Journal of Research and Development. vol. 48, No. 3/4, May/Jul. 2004, pp. 311-322.
P. Mak et al. “Processor Subsystem Interconnect Architecture for a Large Symmetric Multiprocessing System”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 323-337.
T. Webel et al. “Run-Control Migration from Single Book to Multibooks”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 339-346.
D.G. Bair et al. “Functional Verification of the z990 Superscalar, Multibook Microprocessor Complex”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 347-365.
H. W. Anderson et al. “Configurable System Simulation Model Build Comprising Packaging Design Data”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 367-378.
T. M. Winkel et al. “First- and Second-Level Packaging of the z990 Processor Cage”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 379-394.
J. C. Parrilla et al. “Packaging the IBM eServer z990 Central Electronic Complex”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 395-407.
G. F. Goth et al. “Hybrid Cooling With Cycle Steering in the IBM eServer z990”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 409-423.
L. C. Heller “Millicode in an IBM zSeries Processor”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 425-434.
C. Axnix et al. “z990 NetMessage-Protocol-Based Processor to Support Element Communication Interface”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 435-447.
W.E. Chencinski et al. “The Structure of Chips and Links Comprising the IBM eServer z990 I/O Subsystem”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 449-459.
B. Hoppe “Functional Verification of a Frequency-Programmable Switch Chip with Asynchronous Clock Sections”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 461-474.
T. W. Arnold et al. “The IBM PCIXCC: A New Cryptographic Coprocessor for the IBM eServer”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 475-487.
L. W. Wyman et al. “Multiple-Logical-Channel Subsystems: Increasing zSeries I/O Scalability and Connectivity”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 489-505.
G. Banzhaf et al. “SCSI Initial Program Loading for zSeries”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 507-518.
M. L. Fair et al. “Reliability, Availability, and Serviceability (RAS) of the IBM eServer z990”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 519-534.
I. G. Siegel et al. “Logical partition Mode Physical Resource Management on the IBM eServer z990”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 535-541.
W. Gellerich et al. “The GNU 64-Bit PL8 Compiler: Toward an Open Standard Environment for Firmware Development”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 543-556.
S. Koerner et al “The z990 First Error Data Capture Concept”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 557-567.
K. D. Schubert et al. “Accelerating System Integration by Enhancing Hardware, Firmware, and Co-Simulation”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 569-581.
M. Stetter et al “IBM eServer z990 Improvements in Firmware Simulation”, IBM Journal of Research and Development, vol. 48, No. 3/4, May/Jul. 2004, pp. 583-594.

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