Circuit of calculating errata locator and evaluator polynomial,

Details Circuit of calculating errata locator and evaluator polynomial, Circuit of calculating errata locator and evaluator polynomial,

1996-03-20

1998-09-08

Baker, Stephen M.

Excavating

H03M 1300

Patent

active

058056165

ABSTRACT:
The present invention relates to a circuit for calculating an ELP and an EEP, and a Reed-Solomon decoder using the same. The circuit includes: first storage device for storing a syndrome value, coefficient values of the ELP, a discrepancy value and the size of a shortened code; second storage device for storing the coefficient values of the ELP, the reciprocal value of the discrepancy, the discrepancy value, the coefficient values of the ELP and the values obtained by differentiating the coefficient values of the ELP; first selecting device for selectively outputting the values stored in the first storage device in response to first to sixth control signals; second selecting device for selectively outputting the values stored in the second storage device in response to the control signals; multiplication device for multiplying the values selected by the first and second selecting means; third selecting means for selectively outputting the resultant values multiplied by the multiplication device in response to the control signals; third storage device for storing the resultant values selectively output by said third selecting device. Accordingly, the construction of the circuit becomes simple and a chip area can be reduced at the time of integration.

REFERENCES:
patent: 5446743 (1995-08-01), Zook
patent: 5537426 (1996-07-01), Lee
patent: 5583499 (1996-12-01), Oh et al.

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