Circuit of addressing a memory buffer for error correction in a

Details Circuit of addressing a memory buffer for error correction in a Circuit of addressing a memory buffer for error correction in a

1992-11-17

1995-08-08

Envall, Jr., Roy N.

Excavating

367 13, H03M 1300

Patent

active

054405718

ABSTRACT:
An addressing circuit for controlling an address in order to correct an error in case of recording digital data transmitted from a computer on the basis of a DDS (Digital Data Stage) format in a digital audio tape. The addressing circuit has a buffer memory connected to receive digital data transmitted from a host computer, for storing and accessing the digital data supplied by a given control signal, a control signal generating circuit connected to receive a start instruction and a start address from the exterior, for generating a control signal of the buffer memory, and a C3 encoding circuit connected to receive the control signal of the control signal generating circuit, for generating a parity of two symbols with respect to 44 data symbols on the basis of a DDS format.

REFERENCES:
patent: 4805173 (1989-02-01), Hillis et al.
patent: 4873588 (1989-10-01), Hiramatsu
patent: 4890286 (1989-12-01), Hirose
patent: 4914460 (1990-04-01), Hirose
patent: 5163136 (1992-11-01), Richmond
patent: 5253126 (1993-10-01), Richmond
patent: 5287478 (1994-02-01), Johnston et al.
patent: 5293361 (1994-03-01), Aizawa

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