Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2006-08-08
2006-08-08
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S032000, C326S034000, C326S086000
Reexamination Certificate
active
07088128
ABSTRACT:
A circuit module comprises a first circuit chip (102a) and a second circuit chip (102b). Each circuit chip comprises a signal input (104a,104b) and a reference input (106a,106b). A first termination resistance (112) connects the signal inputs (104a,104b) and a second resistance (114) connects the reference inputs (106a,106b). A first termination resistance (116) connects the second signal input (104b) to the termination voltage (120) and a second termination resistance (118) connects the second reference input (106b) to the termination voltage (120). A first ratio between the first resistance (112) and the first termination resistance (116) corresponds to a second ratio between the second resistance (114) and the second termination resistance (118).
REFERENCES:
patent: 5550496 (1996-08-01), Desroches
patent: 6304098 (2001-10-01), Drost et al.
patent: 2004/0264267 (2004-12-01), Nishio et al.
Slater & Matsil L.L.P.
Tran Anh Q.
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