Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-08-02
2005-08-02
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06925624
ABSTRACT:
In accordance with a circuit modification method, when it is determined that an aggressor (2) causes a glitch error in a victim (1), the one or more positions where one or more buffers are to be inserted into the victim (1) are determined based on the coupling capacity Cc between the victim (1) and the aggressor (2). One or more buffers are inserted at one or more internal points of division of the victim (1) which are determined so that the coupling capacity between each of a plurality of wire segments, into which the victim is to be divided by the one or more internal points of division, and the aggressor2is equal to Cc
, where n is the number of wire segments. Furthermore, since the one or more buffers are inserted so that the coupling capacity Cc is properly divided into the coupling capacities between the plurality of wire segments and the aggressor, the amount of glitch to be caused in each of plurality of wire segment can be reduced and no further addition of buffers is needed.
REFERENCES:
patent: 5568395 (1996-10-01), Huang
patent: 6117182 (2000-09-01), Alpert et al.
patent: 6378109 (2002-04-01), Young et al.
patent: 8-102491 (1996-04-01), None
patent: 2000-137554 (2000-05-01), None
R. Levy, et al., “ClariNet: A noise analysis tool for deep submicron design”, p. 233, (http://www.sigda.acm.org/Archives/ProceedingArchives/Dac/Dac2000/papers/2000/dac00/htmfiles/sun_sgi/dacabs.htm#14_1).
Burns Doane , Swecker, Mathis LLP
Levin Naum
Renesas Technology Corp.
Smith Matthew
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