Circuit modeling

Details Circuit modeling Circuit modeling

2001-05-02

2002-12-31

Nguyen, Cuong Quang (Department: 2811)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06502230

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to the field of electrical circuits, and particularly to software suitable for modeling manufacturing processes for the fabrication of semiconductor circuits.
BACKGROUND OF THE INVENTION
Modem digital design of complex circuits and systems, which can contain millions of interconnected gates, involves a number of techniques for managing a design. Tools using computer-aided design (CAD), hardware description languages (HDL), logic synthesis, hierarchy design, and “divide and conquer” strategies such as top-down design are employed.
A hardware description language (HDL) representation of a circuit, such as a Verilog description, is a representation of a circuit in text rather than graphically, enabling a more uniform, portable representation of the circuit, one that can be manipulated by a computer program. HDL may be stylized into “structural” (e.g. at the gate-level), “behavioral” or “dataflow” (typically at the higher level description of a circuit), or any combination of the above. HDL representations are used in logic synthesis, the conversion of a high-level electronic circuit description into a list of logic gates and their interconnections, called the “netlist”.
An HDL description of a system can be written at an intermediate level referred to as a register transfer language (RTL). A subset of RTL that is used by logic synthesis tools (such as Synopsys' DesignCompiler and Cadence's Buildgates) is known as “snythesizable RTL”. A logic synthesis tool with a library of components can convert a RTL description into an interconnection of primitive components that implements the circuit, subject to any specified constraints, such as timing, speed, power consumption and area constraints. Typically these constraints are specified by the designer of the circuit. The output of the logic synthesis tool, after an optimization process referred to as technology mapping, is a so-called netlist of interconnected storage elements, gates, and other functional blocks (note the term net is also a keyword in Verilog, and represents a data type comprising a physical connection between structural elements). The netlist output of the synthesis serves as input to physical design tools that physically place the logic elements and route the interconnections between them to produce a manufacturing circuit layout. When programmable parts are employed, such as field-programmable gate arrays, binary information is produced by design tools to program the logic within the parts.
Hierarchical design involves following an inverted tree in design, with the top-level design of the circuit at the root and more increasingly specific levels of detail at the branches and leaves below. Functional blocks (or modules, where the term module also a keyword in Verilog HDL) are employed at the upper echelons of the tree, while primitive blocks (such as NAND gates) are employed at the lower echelons. In theory the design process is “top down”, where the circuit function is specified by text, with constraints on cost, performance and reliability, and then the circuit is designed by repeatedly dividing it into blocks as necessary. In practice, in order to obtain reusability and to make maximum use of predefined modules, it is often necessary to perform portions of the design bottom up. In addition, bottom up design is sometimes necessary to eliminate violations of constraints in a preliminary specification.
When a gate-level netlist is available, the netlist output serves as input to physical design tools that physically place the logic elements and route the interconnections between them to produce a manufacturing circuit layout. This step, called circuit layout, is unique to semiconductor circuits. Semiconductor components are physical entities in and on a wafer surface, and the dimensions and doping levels of the semiconductor components determine their electrical parameters. Circuit layout, a complicated process performed with the help of sophisticated computer-aided design (CAD) systems, starts with the translation of each of the circuit components of the netlist, and of the primitive components associated with the netlist, into physical dimensions. Physical dimensions can determine how a component behaves. For example, it is known that the resistance of a rectangular bar is given by the formula
R
=
(
ρ
/
t
)
⁢
L
W
,
where &rgr;=the resistivity of the material constituting the rectangular bar, t=the thickness of the bar, L=the length of the bar, and W=width of the bar.
Timing considerations are important in circuit layout as well. If a signal has to traverse too great a distance, it may be necessary to insert a repeater, since a signal is attenuated with distance. Likewise, if a signal has to traverse too short a distance, a buffer has to be inserted or the length of the signal path has to be artificially increased, or else timing with other signals may be skewed. In traditional models, much of the delay has been attributed to transistors, and software models have predicted the delay of such transistors. However, as circuit complexity increases, circuits (and circuit boards) have been formed of several layers (up to ten), with a via (or contact), forming a conducting pathway between two or more substrates (layers). Presently, there are no good software models for accurately predicting the delay caused by vias and wires in an integrated circuit, microchip or printed circuit board.
Therefore, it would be desirable to provide a system and method suitable for modeling electrical circuits in an improved manner.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a system and method of modeling electrical circuits. The present invention may provide improved software for predicting microchip interconnect delays, and in general for an improved semiconductor manufacturing models. Further, the invention may provide for accurate prediction of resistance, capacitance and inductance for interconnections in a semiconductor, allowing for both environmental values and process variations.
In a first aspect of the present invention, a method of predicting a time delay in a semiconductor includes collecting process factor data and environmental condition data for a semiconductor. The collected process factor data and environmental condition data are analyzed to determine a range of adjusted values of at least two of resistance (R), capacitance (C) and inductance (L) for the semiconductor. A time delay for the semiconductor is predicted based upon the determined range of adjusted values of the at least two of resistance (R), capacitance (C) and inductance (L) for an interconnect based upon the process factor data and environmental condition data.
In the second aspect of the present invention, a method of predicting delay in a circuit, includes collecting process factor data and environmental condition data for interconnections. The collected process factor data and environmental condition data is analyzed to determine a range of adjusted values of resistance (R), capacitance (C) and inductance (L) for the interconnections including vias. A time delay for the interconnections including vias is predicted based upon the determined range of adjusted values of the resistance (R), capacitance (C) and inductance (L) for the interconnections based upon the process factor data and environmental condition data.
In a third aspect of the present invention a system suitable for predicting a circuit delay includes an environmental condition determiner suitable for determining environmental condition data that affects calculation of at least one of the resistance (R), capacitance (C) and inductance (L) of an interconnection of a semiconductor. A process value obtainer is included, the process value obtainer suitable for collecting process values that affect calculation of at least one of the resistance (R), capacitance (C) and inductance (L) of an interconnection of a semiconductor. A processor suitable for performing a

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