Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2000-07-14
2003-03-04
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S779000, C257S780000, C257S783000, C438S118000, C438S119000
Reexamination Certificate
active
06528890
ABSTRACT:
TECHNICAL FIELD
The present invention relates to circuits, methods of adhering an integrated circuit device to a substrate, and methods of forming a circuit.
BACKGROUND OF THE INVENTION
Flip chip packages have become increasingly popular for housing integrated circuits and providing electrical connection of integrated circuits with an external substrate. The desire to provide chip assemblies having increased density and durability has broadened the use of flip chips in electronics manufacturing. Conventional flip chip configurations typically include a semiconductor die having a plurality of conductive bumps, such as solder, provided upon bond pads of the chip. The chip is “flipped” over and bonded with the bumps to bond pads of another substrate, thus the term “flip chip.”
In some instances following conductive bonding of the flip chip relative to the substrate, a needle is utilized to deposit an electrically insulative underfill adhesive material adjacent edges of the flip chip. The underfill adhesive material facilitates bonding of the flip chip to the substrate.
In such conventional attachment methods, the dispensing needle is positioned approximately 3 to 5 mils away from the flip chip and 1 to 3 mils off or above the substrate. The underfill material is dispensed onto adjacent sides of the flip chip and allowed to flow or wick under the flip chip. In other words, the deposited underfill material is intended to be received by the sides of the flip chip and flows towards the center of the flip chip.
It is desired that the underfill material substantially fill the volume intermediate the flip chip and the substrate to facilitate a better mechanical connection of the flip chip with the substrate. In particular, the underfill material supplements the electrical interconnections formed by the conductive bumps and the bond pads which also tend to function as mechanical couplings. In preferred configurations, the underfill material tends to alleviate stress imposed upon the electrical connections. Further, the underfill material forms a hermetic seal and provides a flexible buffer material to absorb stress resulting from subsequent high temperature fabrication steps.
The conventional methods of connecting flip chips with external substrates have various drawbacks. For example, a considerable length of time is typically necessary for the underfill material to flow from the deposition sites along adjacent sides of a particular flip chip to areas beneath the flip chip. In addition, a plurality of voids commonly remain intermediate the flip chip and corresponding substrate. Formation of an underfill material layer having plural voids can in some instances provide less than desired sealing. Further, the flip chip and substrate are both exposed to elevated temperatures, such as 80-120 degrees Centigrade, during the underfill wicking process to urge flowing of the underfill materials.
Therefore, a need exists to provide improved connections of flip chips and substrates and improved methodologies of connecting flip chips with substrates.
SUMMARY OF THE INVENTION
The present invention includes circuits, methods of adhering an integrated circuit device to a substrate, and methods of forming a circuit.
A first aspect of the present invention provides an integrated circuit bonding method including the steps of providing an integrated circuit device having a plurality of conductive bumps, and providing an electrically insulative adhesive upon at least a portion, of an outer surface of the integrated circuit device. The method also includes bringing a substrate and the integrated circuit device into proximity with one another. The integrated circuit device bonding method also includes bonding the outer surface of the integrated circuit device to a substrate using the adhesive with at least some of the conductive bumps being in electrical communication with circuitry of the substrate.
Another aspect of the present invention provides a method of forming a circuit. The method includes the steps of providing an integrated circuit device having an outer surface and a plurality of conductive bumps upon the outer surface, and providing a substrate having a plurality of bond pads which correspond to respective ones of the conductive bumps. The method further includes the steps of providing an electrically insulative adhesive over at least a portion of the outer surface of the integrated circuit device and coupling the integrated circuit device and the substrate following the providing of the adhesive. The coupling connects the outer surface of the integrated circuit device with the substrate and forms a plurality of electrical interconnections comprising the conductive bumps and the bond pads.
According to another aspect of the present invention, a circuit comprises an integrated circuit device having an outer surface and a plurality of conductive bumps upon the outer surface. The circuit additionally includes a substrate having an outer surface and a plurality of bond pads upon the outer surface. The bond pads are electrically coupled with the conductive bumps of the integrated circuit device in opposing relation. The outer surface of the integrated circuit device and the outer surface of the substrate define a buffer volume therebetween. The circuit further includes an adhesive which bonds the outer surface of the integrated circuit device and the outer surface of the substrate. The buffer volume has a greater volume of void space than adhesive. Certain aspects of the present invention provide a plurality of discrete adhesive fillets formed about the coupled conductive bumps and corresponding bond pads of the integrated circuit device and the substrate.
The present invention also provides additional structure and methodology aspects.
REFERENCES:
patent: 4732446 (1988-03-01), Gipson et al.
patent: 4835859 (1989-06-01), Beckett
patent: 4984358 (1991-01-01), Nelson
patent: 5019943 (1991-05-01), Fassbender et al.
patent: 5496775 (1996-03-01), Brooks
patent: 5578696 (1996-11-01), Mochizuki et al.
patent: 5726391 (1998-03-01), Iyer et al.
patent: 5834339 (1998-11-01), Distefano et al.
patent: 5872400 (1999-02-01), Chapman et al.
patent: 5897336 (1999-04-01), Broullitte et al.
patent: 5930597 (1999-07-01), Call et al.
patent: 5930599 (1999-07-01), Fujimoto et al.
patent: 5952725 (1999-09-01), Ball
patent: 5956605 (1999-09-01), Akram et al.
patent: 6002172 (1999-12-01), Desai et al.
patent: 6011694 (2000-01-01), Hirakawa
patent: 6061248 (2000-05-01), Otani et al.
patent: 6077725 (2000-06-01), Degani et al.
patent: 6103551 (2000-08-01), Ono et al.
patent: 6222738 (2001-04-01), Maeno et al.
“4-1. Nitto R&D Road Map for Flip Chip Package Materials”;Nitto Denko America, Inc.; Mar. 15, 2000; pps. 1-4.
Kang Donghee
Loke Steven
Wells St. John P.S.
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