Circuit layout device, circuit layout method, and program...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

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07451419

ABSTRACT:
A circuit layout device of a semiconductor integrated circuit having scan chains comprises a circuit layout section for performing the circuit layout of a semiconductor integrated circuit considering a weighting factor being set for a wire of the semiconductor integrated circuit and outputting the layout data, a wire length calculation section for calculating a wire length of a scan chain from the layout data output by the circuit layout section and a wire weighting section for increasing the weighting factor of the scan chain wire based on the scan chain wire length calculated by the wire length calculation section.

REFERENCES:
patent: 7127695 (2006-10-01), Huang et al.
patent: 3-135067 (1991-06-01), None

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