Circuit layout and structure for a non-volatile memory

Details Circuit layout and structure for a non-volatile memory Circuit layout and structure for a non-volatile memory

2006-01-17

2006-01-17

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000, C257S316000, C257S320000, C257S321000, C257S322000, C257S326000

Reexamination Certificate

active

06987298

ABSTRACT:
A structure of non-volatile memory contains a substrate. A plurality of bit lines are formed in the substrate along a first direction, wherein each of the bit lines also serve as a source/drain (S/D) region. A first dielectric layer is disposed over the substrate. A plurality of selection gate (SG) lines are formed over the first dielectric layer between the bit lines. A plurality of charge-storage structure layer are formed over the substrate between the bit lines and the SG lines. A second dielectric layer is formed over the SG lines and a third dielectric layer is formed over the bit lines. A plurality of word lines are formed over the substrate along a second direction, which is crossing the first direction for the bit lines. Wherein, when a selected one of the SG lines is applied a voltage, another S/D region is created in the substrate under the selected one of the SG lines.

REFERENCES:
patent: 6674132 (2004-01-01), Willer
patent: 6898120 (2005-05-01), Natori

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