Circuit layout and semiconductor substrate for...

Details Circuit layout and semiconductor substrate for... Circuit layout and semiconductor substrate for...

2008-01-22

2008-01-22

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07322020

ABSTRACT:
A circuit layout for a photosensitive chip includes a semiconductor substrate, a plurality of first circuit lines and a plurality of second circuit lines. The semiconductor substrate has a matrix of photosensitive units. Each photosensitive unit has a first blocking region, a second blocking region and a photosensitive region formed on the semiconductor substrate. The first blocking region is formed between neighboring photosensitive regions aligned in a vertical direction. The second blocking region is formed between neighboring photosensitive regions aligned in a horizontal direction. Free electrons produced by illuminating the photosensitive units are blocked by the first and the second blocking regions.

REFERENCES:
patent: 6046466 (2000-04-01), Ishida et al.
patent: 2004/0188729 (2004-09-01), Uchida et al.

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