Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Isolation by pn junction only
Reexamination Certificate
1999-03-08
2001-11-20
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Isolation by pn junction only
C438S370000, C257S547000, C257S797000, C257S798000, C257S509000
Reexamination Certificate
active
06319793
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to isolating circuits and more particularly to noise isolation between unrelated circuits on an integrated circuit.
BACKGROUND OF THE INVENTION
Noise isolation between unrelated circuits on an integrated circuit (IC) is highly desirable. This is particularly true when high power circuits and low power circuits are on the same IC. For example, low power circuits may process minimal signals (<10 mV) and cannot tolerate interference generated by high power circuits on the same IC.
FIG. 1
illustrates one of the mechanisms in which coupling occurs between separate functions on the same IC. For example, when digital circuitry
10
switches between high and low states, the change in the inputs and outputs of digital circuitry
10
creates current impulses that are injected into the common substrate
15
via parasitic capacitance C
2
. C
2
represents the total parasitic capacitance that exists between digital circuitry
10
and the common substrate
15
. Transistors within digital circuitry
10
may be used to construct logic devices, such as inverters, NOR gates and AND gates that all contribute to the parasitic capacitance C
2
that allows current to be injected into the common substrate
15
from digital circuitry
10
. The current impulses from the digital circuitry
10
, that are injected in the substrate
15
, flow through substrate
15
. Substrate
15
has a resistance that is represented by resistors R
1
, R
2
and R
3
between digital circuitry
10
and ground connections
20
,
25
of the IC.
The current flow that is coupled through resistance R
1
from digital circuitry
10
via parasitic capacitance C
2
causes voltage noise that is coupled to analog circuitry
30
through parasitic capacitance C
1
. This noise coupling mechanism causes noise within analog circuitry
30
which limits the minimal signal voltages that can be processed by analog circuitry
30
when analog circuitry
30
is placed on the same IC (same substrate) as digital circuitry
10
.
The distribution of the current flow, and hence the amount of coupled noise, is dependent on the values of resistances of R
1
, R
2
, and R
3
. If R
1
is decreased relative to R
2
and R
3
, more noise voltage is coupled to analog circuitry
30
. When epitaxial wafers are used, the substrate normally has a lower resistance so that cross-talk problems are increased.
Currently, two basic substrate architectures exist for standard CMOS processing: bulk substrate wafers and epitaxial layered wafers. Bulk substrate wafers consist of silicon that is uniformly doped to a constant carrier concentration. Epitaxial layered wafers have a base of substrate layer that is a heavily doped layer and a lightly doped epitaxial layer. The light doping of the epitaxial layer emulates the surface background carrier concentration similar to that of the bulk substrate wafers. The heavily doped substrate layer provides a low impedance connection (R
1
), and thus more severe noise coupling occurs between analog circuitry
30
and digital circuitry
10
.
Many alternatives exist to decrease the noise coupling through a common substrate. One alternative is to manufacture digital and analog circuits on separate ICs. This adds cost due to separate packaging and increased pin counts. Another alternative utilizes special processing steps, such as dielectric or junction isolation, that physically isolate unrelated circuits. However, these steps are costly compared to standard CMOS processes. Other alternatives rely on circuit design techniques, such as current-mode logic, or spacing of the unrelated circuits, but circuit noise isolation is still difficult to achieve using these alternatives.
It is against this background, and the limitations and problems associated therewith, that the present invention has been developed.
SUMMARY OF THE INVENTION
The present invention includes an integrated circuit that has a common substrate and at least two circuits, such as one or more low power circuits and one or more high power circuits. The substrate is preferably derived from a bulk substrate wafer. The integrated circuit preferably comprises at least two islands in the substrate layer that provide low resistance paths to the ground potential. These two islands are buried-layers that are implanted, by preference, using conventional high energy MeV implantation techniques.
The present invention also includes a method of manufacturing an integrated circuit including a substrate and at least two circuits. The method comprises the step of implanting at least two islands in the substrate for noise isolation between the circuits. The implanting can be accomplished using conventional masking and high-energy implantation, preferably MeV energy implantation.
The present invention may therefore comprise a method of isolating circuits to be formed on a common substrate of a wafer comprising the steps of masking predetermined locations on said wafer, irradiating the wafer with ions having an energy level sufficient to implant the ions in embedded regions of the common substrate so that portions of said embedded regions are substantially aligned with unmasked portions of the wafer so that isolation regions are formed between the embedded regions and the embedded regions are buried in the common substrate so that a portion of the common substrate separates the embedded regions from the circuits.
The present invention may also comprise a method of isolating circuits to be formed on a common substrate of a wafer comprising the steps of forming a mask in predetermined locations on the wafer that are substantially over the isolation regions between the circuits, irradiating the wafer with ions in the range of approximately 1 MeV-3 MeV to implant the ions in embedded regions of the common substrate so that the isolation regions are formed between the circuits and the embedded regions are buried in the common substrate substantially under said circuits.
The present invention may further comprise a method of isolating circuits to be formed on a common substrate of a wafer comprising the steps of forming a mask in predetermined locations on the wafer that are aligned with isolated regions between the circuits, irradiating the wafer with ions having an energy level sufficient to implant the ions in embedded regions of the common substrate that are substantially aligned with unmasked portions of the wafer so that the isolated regions are formed between the circuits and the embedded regions are buried in the common substrate and have a lower resistance than the common substrate so that currents injected into the common substrate by a particular circuit preferentially flow to a ground potential of the particular circuit rather than through the isolation region that has a higher resistance.
The present invention may further comprise an integrated circuit having a plurality of circuits formed on a common substrate that are isolated by isolation regions in the common substrate between the circuits, the integrated circuit made by the process of masking predetermined locations of the common substrate that are substantially aligned with the isolation regions with a material that is capable of masking high energy ions, irradiating the common substrate with the high energy ions such that the high energy ions have an energy level sufficient to implant the high energy ions in embedded regions of the common substrate that are aligned with unmasked portions of the common substrate, said unmasked portions being aligned with the circuits so that the isolation regions are formed between the embedded regions and the embedded regions are buried in the common substrate so that a portion of the common substrate separates the embedded regions from the circuits.
The present invention may further comprise an integrated circuit comprising a common substrate having low doping and a first predetermined resistance, circuitry formed on predetermined portions of the common substrate, embedded regions of the common substrate that are implanted with ions such th
Bartlett Donald M.
Mason Randall J.
Miller Gayle W.
Blum David S
Bowers Charles
Cochran & Collins, L.L.P.
LSI Logic Corporation
LandOfFree
Circuit isolation utilizing MeV implantation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit isolation utilizing MeV implantation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit isolation utilizing MeV implantation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2601157