Circuit having a control array of memory cells and a current sou

Details Circuit having a control array of memory cells and a current sou Circuit having a control array of memory cells and a current sou

1994-07-15

1995-10-03

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Data refresh

365203, 365210, G11C 700

Patent

active

054558018

ABSTRACT:
A method and circuit for generating a self-refresh mode signal and a self-refresh cycle signal. The circuit is a dynamic random access memory (DRAM) device having a control array of control cells charged to a potential by a current source and having a monitor circuit for monitoring the potential of the control array. The DRAM comprises a discharge circuit which discharges the potential of the control array in response to the monitor circuit detecting when the potential of the control array has reached a trip point. A counter circuit counts the number of cycles of charge and discharge and generates the self-refresh mode signal after a desired count is reached. The counter circuit continues to count the number of cycles of charge and discharge while in the refresh mode and generates a self-refresh cycle signal each time the counter circuit counts a desired number of counts.

REFERENCES:
patent: 4682306 (1987-07-01), Sakurai et al.
patent: 4982369 (1991-01-01), Tatematsu
patent: 5375093 (1994-12-01), Hirano
patent: 5392251 (1995-02-01), Manning

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