Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-21
2005-06-21
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06910199
ABSTRACT:
A group based design methodology and system. In one embodiment the groups have predefined layout characteristics and are sometimes amalgamated into functions. Integrated circuits are designed by placing groups and functions into a layout space.
REFERENCES:
patent: 4584653 (1986-04-01), Chih et al.
patent: 4701860 (1987-10-01), Mader
patent: 5031111 (1991-07-01), Chao et al.
patent: 5124776 (1992-06-01), Tanizawa et al.
patent: 5388055 (1995-02-01), Tanizawa et al.
patent: 5490103 (1996-02-01), Haraguchi et al.
patent: 5502644 (1996-03-01), Hamilton et al.
patent: 5598344 (1997-01-01), Dangelo et al.
patent: 5623417 (1997-04-01), Iwasaki et al.
patent: 5623418 (1997-04-01), Rostoker et al.
patent: 5666289 (1997-09-01), Watkins
patent: 5671397 (1997-09-01), Crafts
patent: 5761078 (1998-06-01), Fuller et al.
patent: 5801958 (1998-09-01), Dangelo et al.
patent: 5847968 (1998-12-01), Miura et al.
patent: 5867399 (1999-02-01), Rostoker et al.
patent: 5870308 (1999-02-01), Dangelo et al.
patent: 5880971 (1999-03-01), Dangelo et al.
patent: 5910897 (1999-06-01), Dangelo et al.
patent: 5933356 (1999-08-01), Rostoker et al.
patent: 5963454 (1999-10-01), Dockser et al.
patent: 5984510 (1999-11-01), Guruswamy et al.
patent: 5994946 (1999-11-01), Zhang
patent: 6011911 (2000-01-01), Ho et al.
patent: 6182272 (2001-01-01), Andreev et al.
patent: 6298468 (2001-10-01), Zhen
patent: 6397375 (2002-05-01), Block et al.
patent: 6467074 (2002-10-01), Katsioulas et al.
patent: 6477690 (2002-11-01), Witte et al.
patent: 6532580 (2003-03-01), Josephson et al.
“DesignWare Foundation Library,” Synopsys, Inc., pp. 1-5.
“CBAll Design System Tools,” Synopsys, Inc., www.synopsys.com/products/siarc/des_sys_ds.html, pp. 1-7.
“Synopsys and Infineon,” Synopsys, Inc., www.synopsys.com/products/designware/designware.html, pp. 1-2.
“Synopsys Adds Silicon Libraries and Additional Macrocells to DesignWare(R),” Synopsys, Inc., www.synopsys.com
ews/announce/press2000/sil_lib_pr.html, pp. 1-4.
“A First Tool of SpecGen™ Series : Designing from System Specification,”VisualSpec, Y Explorations, Inc. (Irvine, CA), two pages.
S. Posluszny, et al., “‘Timing Closure by Design,’ A High Frequency Microprocessor Design Methodology,” IBM Austin Research Lab (Austin, TX), six pages.
Bowers Brandon
Telairity Semiconductor, Inc.
Thompson A. M.
Townsend and Townsend / and Crew LLP
LandOfFree
Circuit group design methodologies does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit group design methodologies, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit group design methodologies will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3466113